Resources

• Design Security Overview with Microsemi FPGAs and SoCs
• Data Security Overview with Microsemi FPGAs and SoCs
• Securing Your Supply Chain Life Cycle
• Timing over MACsec
• Overview of Supply Chain Assurance of Intelligent ICs

News

• Microsemi and Intrinsic-ID Team Up to Deliver Secure Boot Solution for Electronic Systems in the Government, Aerospace and Defense Markets
• Microsemi and Thales e-Security Announce Hardware Security Module Reseller Agreement to Protect Customer Revenue
• Microsemi and Athena Announce FPGA Cores with Strong DPA Countermeasures for Cryptography Users
• Microsemi Collaborates with HMS Industrial Networks AB to Introduce Highly Secure Anybus CompactCom 40 Industrial Protocol Solutions
• Microsemi Hosts 4th Annual Security Forum to Address Rapidly Evolving Cyber Security Threats

How 1588 Works

How Does 1588 Work?

The 2008 version of the protocol defines different clock classes and the syntactic language between these classes of clocks.

• A Master Clock, when selected via the best master clock algorithm, provides the time base to all clocks in its domain;
• The Primary Reference Time Clock (PRTC) is another clock class whose value of the time base is periodically captured with timestamps – usually once every second. The PRTC receives its own timing from an atomic clock either directly or via GPS satellites. The time stamps created represent the current value of time at the PRTC.
• Ordinary clocks comprise the clock class that receives and uses the timestamps to produce clock signals for applications

Using the 1588 protocol, timestamps are inserted into “sync” packets in specially defined fields, which are  forwarded into the network as Ethernet or IP packets using user datagram protocol (UDP) as the packet type.

The master sends a 1588 frame called the “Sync” message, inserting a time stamp at the time stamping point. The slave receives the Sync message with the time stamp inserted by the master clock. For frequency recovery, this is all that is needed for the algorithm to derive a frequency reference. For applications requiring phase and time-of-day (ToD), such as LTE-Advanced or 5G in telecom networks, the slave must be able to measure the packet flight time from master to slave in order to synchronize the 1 PPS rollover between the master and slave and calculate the time at the slave. To do so, the slave sends a “Delay_Request” message back to the master. The delay request message does not include a time stamp, it simply remembers the time it sent the Delay_Request message. The master then sends back a “Delay_Response” message which contains the time at which the master received the Delay_Request message. From these four time stamps collectively, the slave can now derive the packet flight time.

The 1588 protocol assumes network path symmetry and that the packet flight time of the upstream and downstream paths between the grandmaster clock and ordinary clocks are equal. In reality, three types of delay components affect the path delay in each direction:

• Link distance;
• Serialization; and
• Packet delay variation

Link distance and serialization rate offsets are the two static asymmetry components, meaning that they don’t change and are “invisible” to the algorithm in the ordinary clock. Careful network engineering can minimize both these types of impairments.

The third delay component is the actual variation in packet delay propagation as packets pass thru the intermediate nodes between the grandmaster and ordinary clocks. This packet delay variation (PDV) is the chief cause of 1588 ordinary clock computation errors.

Understanding Boundary Clocks & Transparent Clocks

The 2002 version of the standard was created for use on single segment Ethernet LANs. It was prohibited for “sync” packets from a grandmaster clock to “cross” LAN boundaries. The 1588 Boundary Clock (BC) was designed to straddle the interface between two Ethernet LANs. The side of the BC on the LAN interface with the grandmaster clock operates as an ordinary clock. The side of the BC on the other side of the LAN segment interface acts as a grandmaster to the ordinary clocks on that segment.

The PDV of a single segment LAN is non-existent, so the BC was able to transfer the time base of the true grandmaster to its community of ordinary clocks with virtually no phase or frequency offset. The BC also prevented the cross segment ordinary clocks from “seeing” the actual grandmaster and this reduced the load on that clock.

The Transparent Clock (TC) was created for the updated IEEE 1588-2008 version of the standard in recognition of the fact that 1588 packets would be traveling over large networks with multiple intermediate nodes between the grandmaster clock and the ordinary clock. It was also understood these intermediate nodes would add PDV to the flight times of each packet, which could result in a flight time asymmetry on the upstream and downstream paths.

Two versions of the TC were defined: end-to-end and peer-to-peer. The TC is “transparent” to the transport network protocol used by 1588. As the various TC components “measure” the delays in the nodes and links, these measured values are placed in a 1588 packet field named the “correction” field.

As each pair of TC components makes a time measurement, the result is “added” to the correction field. These time measurements are expressed in nanoseconds. When the 1588 packet arrives at its targeted ordinary clock the 1588 protocol calls for the clock to extract the contents of the correction field and subtract the correction field value from the computed flight time derived by the difference in time base value between the “master” and ordinary clocks time bases.

The expected result of this process is a drastic reduction in realized PDV making the ordinary slave clocks filtering algorithm less complex and less costly.

IEEE 1588 is currently the only standardized terrestrial mechanism to deliver phase/time via a packet-based network with nanosecond accuracy.

1588 Profile Support

IEEE 1588 Profile Support

Microsemi's comprehensive systems, IC and software solutions portfolio supports multiple key IEEE 1588 profiles for frequency, phase and power including:

• Frequency Profile: ITU-T G.8265.1 Telecom Profile for Frequency, complemented by ITU-T G.8263 Packet Equipment Clocks
• Phase Profile: ITU-T G.8275.1 Telecom Profile for Phase, complemented by ITU-T G.8273.2 Boundary Clock and G.8273.4 Telecom Time Slave Clocks for applications with less than 1 μs accuracy requirements
• Power Profile: IEEE C37.238-2011 Power Profile, Grandmaster, Boundary Clock, and Ordinary Clock for industrial and power (smart grid) applications

Solutions

IEEE 1588 Portfolio

Microsemi offers a comprehensive, industry leading, end-to-end IEEE 1588 product portfolio with choice of higher integration or flexible implementation for a variety of applications. Microsemi's 1588 solutions are field-proven in networks worldwide, and include complete systems for carriers and service providers, as well as ICs used to make IEEE 1588-compliant Ethernet Switches and end nodes that require synchronization.

For Telecom Service Providers

• IEEE 1588 PTP source / master equipment (Grand Masters): Microsemi Grand Masters support various capabilities of PTP, NTP and other timing protocols. Our portfolio includes range of timing equipment supporting various input and output connections, number of clients as well as form factors. These serve a variety of end markets including wireless and wireline infrastructure, cable, smart grid/power line as well as data center applications. Our newest timing system, Integrated Grand Master (IGM), integrates an indoor GPS receiver and antenna in compact form factor ideally suited to deploy in small cell and HetNet scenarios.
• Precision crystal oscillators, including OCXO, TXCO, and VCXO, and atomic clocks for holdover timing
• NTP servers
• Software: TimePictra Software Suite enables service providers to see a complete picture of timing and synchronization in their networks.

For OEMs Designing Telecom Equipment

• Ethernet PHYs: Ethernet PHYs with highly accurate IEEE 1588 time stamp, including 128-bit MACsec (802.1AE-2006) and 256-bit MACsec (802.1AEbn-2011). This is the industry's only secure 1588 solution with simultaneous timestamping and MACsec support with no loss to 1588 accuracy
• Network Synchronization ICs: High accuracy, low jitter PLLs
• Software. Microsemi's highly evolved servo algorithm extracts accurate timing in complex networks with multiple hops and asymmetry of the network and PTP stack
• Timing Synchronization Module (TSM): Microsemi's IEEE 1588 TSM consist of hardware devices, software and firmware. It combines Microsemi's expertise across FPGAs, 1588 PLLs, Ethernet PHYs devices, PTP Engine and Time-synchronization algorithm. The solution provides nanosecond level timestamping accuracy across the network.      

Ready to learn more? Contact your local Microsemi sales office to find the right products and technologies for your IEEE 1588 timing and synchronization needs.

Resources

Brochures/Datasheets

• High Performance Rubidium Oscillators
• Cesium Atomic Clocks to Backup GNSS_GPS Receivers in Communications Networks 

Webinars

• SA.45s CSAC Chip Scale Atomic Clock 

White Papers

• Shock and Vibration Testing of the SA.45s Chip Scale Atomic Clock (CSAC) Validation Build Units
• Rubidium Sync Holdover Ensures Mobile Service Availability