MT9041
Single Reference Frequency Selectable Digital PLL with Multiple Clock Outputs for T1/E1 Trunk and Backplane Synchronization
Overview
The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a 2.048 MHz, 1.544 MHz, or 8 kHz input reference. The MT9041B is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced, Stratum 4, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications.
Features & Benefits
- Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces
- Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces
- Selectable 1.544 MHz, 2.048 MHz or 8 kHz input reference signals
- Provides C1.5, C2, C3, C4, C8 and C16 output clock signals
- Provides 3 different styles of 8 KHz framing pulses
- Attenuates wander from 1.9 Hz
Resources
Documentation
Application Notes
- ZLAN-68 - List of Oscillators & Crystals that can be used with Microsemi's PLL, Digital Switches with Embedded PLL & Timing over Packet Devices
- ZLAN-71-Applications of the Digital PLLs Design Guidelines for Using Oscillators
- MSAS-74 - MT9041 and MT9041B Differences
Downloads, Firmware and Drivers
- IBIS Models:
- Mt9041bp
Applications
Typical Applications
- Synchronization and timing control for multitrunk T1 and E1 systems
- ST-BUS clock and frame pulse sources
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