ZL30409
Dual Reference Frequency Selectable, 3.3 V Digital PLL with Multiple Clock Outputs for T1/E1 and Stratum 4 and 4E Applications, with Stratum 3 Holdover
Overview
The ZL30409 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connectivity during temporary synchronization interruptions
Features & Benefits
- Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
- Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces
- Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8 kHz input reference signals
- Provides 5 styles of 8 KHz framing pulses
- Stratum 3 holdover frequency accuracy of 0.02 PPM
- Holdover indication
- Attenuates wander from 1.9 Hz
- Fast lock mode
- Provides Time Interval Error (TIE) correction
- Accepts reference inputs from two independent sources
- JTAG Boundary Scan
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Resources
Documentation
Application Notes
- ZLAN-68 - List of Oscillators & Crystals that can be used with Microsemi's PLL, Digital Switches with Embedded PLL & Timing over Packet Devices
- ZLAN-71-Applications of the Digital PLLs Design Guidelines for Using Oscillators
Applications
Typical Applications
- Synchronization and timing control for Customer Premises Equipment (CPE)
- ST-BUS clock and frame pulse sources
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