MT9040
Single Reference Frequency Selectable, 3.3 V Digital PLL with Multiple Clock Outputs for Stratum 4 Applications
Overview
The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. The MT9040 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048 MHz, 1.544 MHz, or 8 kHz input reference. The MT9040 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter transfer, intrinsic jitter, frequency accuracy and capture range for these specifications.
Features & Benefits
- Supports AT&T TR62411 and Bellcore GR-1244-CORE and Stratum 4 timing for DS1 interfaces
- Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces
- Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or 8 kHz input reference signals
- Provides C1.5, C2, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals
- Provides 5 different styles of 8 KHz framing pulses
- Attenuates wander from 1.9 Hz
- Fast lock mode
- JTAG Boundary Scan
Resources
Documentation
Application Notes
- ZLAN-68 - List of Oscillators & Crystals that can be used with Microsemi's PLL, Digital Switches with Embedded PLL & Timing over Packet Devices
- ZLAN-71-Applications of the Digital PLLs Design Guidelines for Using Oscillators
Applications
Typical Applications
- Synchronization and timing control for multitrunk T1 and E1 systems
- ST-BUS clock and frame pulse source
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