Memory

DDR Controller

In SmartFusion2 and IGLOO2, MDDR and Fabric DDR (FDDR) are two hardened ASIC blocks for interfacing the DDR2, DDR3, and LPDDR1 memories. The MDDR and FDDR subsystems are used to access DDR memories for high-speed data transfers and code execution. These subsystems include a DDR memory controller, DDR PHY, and arbitration logic to support multiple masters. 

In SmartFusion2, the DDR Memory connected to the MDDR subsystem can be accessed by the MSS Masters and master logic implemented in the FGPA fabric (FPGA fabric master).

In IGLOO2, the DDR Memory connected to the MDDR subsystem can be accessed by the high-performance memory subsystem (HPMS) masters and master logic implemented in the FPGA fabric (FPGA fabric master).

The FPGA fabric masters communicate with the DDR memories interfaced to the FDDR subsystem through AXI or AHB interfaces.

Key Features

• Integrated on-chip DDR memory controller and PHY
• Configurable to support LPDDR1, DDR2, and DDR3 memory devices
• Up to 667 Mbps (333.33 MHz DDR) performance
• Supports memory densities up to 4 GB
• Supports 8-/16-/32-bit DDR standard dynamic random access memory (SDRAM) data bus-width modes
• Supports a maximum of 8 memory banks
• Supports single rank of memory
• Optional Single error correction and double error detection (SECDED) mode
• Supports DRAM burst lengths of 4, 8, or 16, depending on configured bus-width mode and DDR type 

MDDR Block Diagram

Soft MC

Apart from the hard IP blocks for the commonly used memories, Soft Memory Controllers are available as IP cores for other type of memories i.e. QDR and are implemented in the FPGA fabric. Microsemi enhances design productivity by providing an extensive suite of optimised soft memory controller IP cores for use with Microsemi FPGAs and SoC FPGAs.

Soft Memory Controller

The SmartFusion2 and IGLOO2 soft memory controller fabric interface controller (SMC_FIC) is used to access external bulk memories other than DDR through the FPGA fabric. The SMC_FIC can be used with a soft memory controller for the Microcontroller Subsystem (MSS)/High Performance Memory Subsystem (HPMS) to access memories such as SDRAM, flash and SRAM.

CoreMMC

CoreMMC provides a Multimedia Card (MMC) controller to interface external MMC flash and eMMC devices. The controller allows storing boot images and booting the processor from the removable flash card. The flash card can also be used to expand the on-board storage capacity for larger applications or to store user data.

CoreQDR

CoreQDR provides a soft controller for interfacing with Quad data rate (QDR), QDR II or QDR II+ SRAMs. Quad data rate synchromous dynamic random access memories (SDRAMs) are a family of SRAMS with separate read and write channels, each operating at double data rate (DDR), optimised for high-performance communications applications such as the data plane memory of routers. QDR SDRAM performs functions such as packet buffering, statistics counting, and flow rate control. 

CoreSDR

CoreSDR provides a high-performance interface to single-data-rate (SDR) synchronous dynamic random access memory (SDRAM) devices. CoreSDR accepts read and write commands using the simple local bus interface and translates these requests to the command sequences required by SDRAM devices. CoreSDR uses bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to four banks can be managed at one time. Access cascading is also supported; allowing read or write requests to be chained together. This results in no delay between requests, enabling up to 100% memory throughput for sequential accesses. 

Getting Started

Software Tools

Hardware Tools

• PolarFire Evaluation Kit:- Microsemi offers a 300K LE PolarFire-based kit with DDR4, DDR3 and SPI-flash for a broad class of applications, that is ideally suited for high-speed transceiver evaluation, 10Gb Ethernet, IEEE1588, JESD204B, SyncE, SATA and more. 

• SmartFusion2 Advanced Development Kit - Microsemi offers 150K LE device inherently integrates reliable flash-based FPGA fabric, a 166 MHz Cortex™-M3 processor digital signal processing (DSP) blocks, static random-access memory (SRAM), embedded nonvolatile memory (eNVM), and industry-required high-performance communication interfaces— all on a single chip.

• The SmartFusion2 Security Evaluation Kit - provides the low-cost platform to evaluate design and data security features offered by the SmartFusion2 devices. Evaluation board features M2S090TS-FGG484 90K LE device and includes various high speed  interfaces like PCIe Gen2x1, four SMA connectors for SERDES, RJ45 for 10/100/1000 Ethernet. Current measurement test points have been provided to evaluate the low-power capabilities of the device. Using SmartFusion2 device features and on-board resources, kit helps in quick prototyping of low-power, secure and highly integrated applications.

• SmartFusion2 Starter Kit - provides a cost effective platform for evaluation and development of a SmartFusion2 SoC FPGA based solution. The kit utilizes a miniature mezzanine form factor system-on-module, which integrates the SmartFusion2 device with 64MB LPDDR, 16MB SPI Flash and Ethernet PHY. The baseboard provides easy to use benchtop access to the SmartFusion2 SoC and interfaces

• IGLOO2 Evaluation Kit provides a cost effective platform for evaluation and development of an IGLOO2 FPGA based solution.

Demos and User Guides

• UG0676: PolarFire FPGA Memory Controller User Guide
  

Applications

Featured Applications for Memory

Engine Systems & Controls

RF & Microwave Systems