IGLOO2 FPGAs
More Resources in Low Density Devices
Overview
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These flash FPGA devices are ideal for general purpose functions such as Gigabit Ethernet or dual PCI Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management and secure connectivity. Microsemi FPGAs are used by customers in Communications, Industrial, Medical, Defense, and Aviation markets. |
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More Resources in Low Density Devices
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IGLOO2 FPGA Architecture
IGLOO2 FPGAs offer 5K-150K LEs with a high performance memory subsystem, up to 512KB embedded flash, 2 x 32 KB embedded static random-access memory (SRAM), two direct memory access (DMA) engines and two double data rate (DDR) controllers. Architecture highlights include:
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Product Tables
Product Family
| Features | M2GL005 | M2GL010 | M2GL025 | M2GL050 | M2GL060 | M2GL090 | M2GL150 | |
|---|---|---|---|---|---|---|---|---|
| Logic/DSP | Maximum Logic Elements (4LUT + DFF)* | 6,060 | 12,084 | 27,696 | 56,340 | 56520 | 86,316 | 146,124 |
| Math Blocks (18x18) | 11 | 22 | 34 | 72 | 72 | 84 | 240 | |
| PLLs and CCCs | 2 | 6 | 8 | |||||
| SPI/HPDMA/PDMA | 1 each | |||||||
| Fabric Interface Controllers (FICs) | 1 | 2 | 1 | 2 | ||||
| Security | AES256, SHA256, RNG | AES256, SHA256, RNG, ECC, PUF | ||||||
| Memory | eNVM (K Bytes) | 128 | 256 | 512 | ||||
| LSRAM 18K Blocks | 10 | 21 | 31 | 69 | 69 | 109 | 236 | |
| uSRAM1K Blocks | 11 | 22 | 34 | 72 | 72 | 112 | 240 | |
| eSRAM (K Bytes) | 64 | |||||||
| Total RAM (K bits) | 703 | 912 | 1104 | 1826 | 1826 | 2586 | 5000 | |
| High Speed | DDR Controllers | 1x18 | 2x36 | 1x18 | 1x18 | 2x36 | ||
| SERDES Lanes | 0 | 4 | 8 | 4 | 4 | 16 | ||
| PCIe End Points | 0 | 1 | 2 | 4 | ||||
| User I/Os | MSIO (3.3V) | 115 | 123 | 157 | 139 | 271 | 309 | 292 |
| MSIOD (2.5V) | 28 | 40 | 40 | 62 | 40 | 40 | 106 | |
| DDRIO (2.5V) | 66 | 70 | 70 | 176 | 76 | 76 | 176 | |
| Total User I/O | 209 | 233 | 267 | 377 | 387 | 425 | 574 | |
| Grades | Commercial (C), Industrial (I), Military (M), Automotive(T1/T2)* | C,I,T1,T2 | C,I,M,T1,T2 | C,I,M,T1,T2 | C,I,M,T1,T2 | C,I,M,T1,T2 | C,I,M,T1,T2 | C,I,M |
| * Total logic may vary based on utilization of DSP and memories in your design. Please see the IGLOO2 Fabric UG for details * Automotive grade is available only in VF256, VF400, FG484, FG676 and TQ144 packages |
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Packaging and I/Os
| Type | FCS325 | VF256 | FCS536 | VF400 | FCV484 | TQ144 | FG484 | FG676 | FG896 | FC1152 | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Pitch (mm) | 0.5 | 0.8 | 0.5 | 0.8 | 0.8 | 0.5 | 1.0 | 1.0 | 1.0 | 1.0 | ||||||||||
| L x W (mm) | 11x11 | 14x14 | 16x16 | 17x17 | 19x19 | 20x20 | 23x23 | 27x27 | 31x31 | 35x35 | ||||||||||
| Device | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes | I/O | Lanes |
| M2GL005 | 161 | - | 171 | - | 84 | - | 209 | - | ||||||||||||
| M2GL010 | 138 | 2 | 195 | 4 | 84 | - | 233 | 4 | ||||||||||||
| M2GL025 | 180 | 2 | 138 | 2 | 207 | 4 | 267 | 4 | ||||||||||||
| M2GL050 | 200 | 2 | 207 | 4 | 267 | 4 | 377 | 8 | ||||||||||||
| M2GL060 | 200 | 2 | 207 | 4 | 267 | 4 | 387 | 4 | ||||||||||||
| M2GL0901 | 180 | 4 | 267 | 4 | 425 | 4 | ||||||||||||||
| M2GL150 | 293 | 4 | 248 |
4 |
574 | 16 | ||||||||||||||
* If you do not find the package or features you are looking for here please contact soc_marketing@microsemi.com.
Documentation
Showing 116 Documents
Application Notes
Low Power
AC412: IGLOO2 FPGA Flash*Freeze Entry and Exit - Libero SoC v12.5 Application Note
- Design Files [ ZIP, 20.7 MB ]
1.5 MB
09/2020
DSP
High-Speed Serial Interface
AC437: Implementing PCIe Reset Sequence in SmartFusion2 and IGLOO2 Devices - Libero SoC v11.8 SP3 Application Note
- Design Files [ RAR, 314 MB ]
- Programming Files [ RAR, 314 MB ]
1.22 MB
02/2018
Security
AC407: Using NRBG Services in SmartFusion2 and IGLOO2 Devices - Libero SoC v11.8 Application Note
- SmartFusion2 Design Files [ RAR, 67.8 MB ]
- IGLOO2 Design Files [ RAR, 67.8 MB ]
968.16 kB
05/2017
AC410: Using AES System Services in SmartFusion2 and IGLOO2 Devices - Libero SoC v11.8 Application Note
- Design Files [ RAR, 213 MB ]
- Programming Files [ RAR, 213 MB ]
1003.77 kB
04/2017
AC406: Configuring IGLOO2 and SmartFusion2 Devices for Safety-Critical Applications Application Note
5.39 MB
12/2019
AC432: Using SHA-256 System Services in SmartFusion2 and IGLOO2 Devices - Libero SoC v11.8 Application Note
- Design Files [ RAR, 320 MB ]
977.11 kB
05/2020
AC433: Using Zeroization in SmartFusion2 and IGLOO2 Devices - Libero SoC v11.6 Application Note
- Design Files [ RAR, 173 MB ]
2.91 MB
10/2015
Memory/Controller
AC421: IGLOO2 FPGA SRAM Initialization from eNVM - Libero SoC v11.7 Application Note
- Design Files [ RAR, 58.3 MB ]
1.37 MB
02/2016
AC424: IGLOO2 - Optimizing DDR Controller for Improved Efficiency - Libero SoC v11.6 Application Note
- Design Files [ RAR, 27.2 MB ]
3.08 MB
10/2015
AC429: SmartFusion2 and IGLOO2 - Accessing eNVM and eSRAM from FPGA Fabric - Libero SoC v11.8 Application Note
- Design Files [ RAR, 94.3 MB ]
5.62 MB
03/2017
AC425: Using DSN, User Design Version, and NVM Data Integrity Check Services in IGLOO2 Devices Application Note
- Design Files [ ZIP, 21.1 MB ]
4.95 MB
03/2021
AC428: SmartFusion2 and IGLOO2 - DDR Low Power Modes - Libero SoC v11.7 Application Note
- Design Files [ RAR, 27.8 MB ]
2.93 MB
02/2016
Others
Migration
Programming
No Documents Available.
Characterization Reports
High-Speed Serial Interface
Configuration Guides
Low Power
No Documents Available.
DSP
No Documents Available.
High-Speed Serial Interface
Security
No Documents Available.
Memory/Controller
Others
No Documents Available.
Migration
No Documents Available.
Programming
HPMS
Datasheets
Demo / Reference Designs
Low Power
2.94 MB
03/2016
DSP
2.14 MB
03/2017
2.56 MB
04/2016
4.02 MB
12/2014
High-Speed Serial Interface
DG0532: IGLOO2 FPGA PCIe Control Plane with Device Serial Number - Libero SoC v11.8 SP1 Demo Guide
- Design Files [ RAR, 193 MB ]
5.95 MB
09/2017
1.78 MB
06/2020
6.2 MB
03/2016
DG0517: SmartFusion2 and IGLOO2 PCIe Data Plane Demo using 2 Channel Fabric DMA - Libero SoC v11.8 Demo Guide
- Design Files [ RAR, 327 MB ]
7.1 MB
04/2017
5.34 MB
01/2017
Security
No Documents Available.
Memory/Controller
Others
No Documents Available.
Migration
No Documents Available.
Programming
DG0681: IGLOO2 FPGA In-Application Programming Using PCIe Interface - Libero SoC v11.7 Demo Guide
- Design Files [ RAR, 59.3 MB ]
4.02 MB
05/2016
Errata
Kit User Guides
Pinout / Packaging
Power Calculators
Product Brochures
Quality & Reliability Reports
Silicon User Guides
Low Power
DSP
No Documents Available.
High-Speed Serial Interface
Security
Memory/Controller
Others
Migration
No Documents Available.
Programming
HPMS
Tutorials
Low Power
No Documents Available.
DSP
TU0312: DSP Flow for SmartFusion2 and IGLOO2 Devices - Libero SoC v11.7 Quickstart and Design Tutorial
- Design Files for SmartFusion2 [ RAR, 27.7 MB ]
- Design Files for IGLOO2 [ RAR, 27.7 MB ]
3.68 MB
04/2016
High-Speed Serial Interface
TU0509: Implementing PCIe Control Plane Design in IGLOO2 FPGA - Libero SoC v11.8 SP1 Tutorial
- Design Files [ RAR, 256 MB ]
18.37 MB
09/2017
TU0570: Implementing a SmartFusion2 and IGLOO2 SERDES EPCS Protocol Design - Tutorial
- IGLOO2 Design Files [ ZIP, 129 MB ]
- SmartFusion2 Design File [ ZIP, 129 MB ]
33.82 MB
01/2021
Security
Memory/Controller
No Documents Available.
Others
No Documents Available.
Migration
No Documents Available.
Programming
TU0530: SmartFusion2 and IGLOO2 SmartDebug Hardware Design Debug Tools - Libero SoC v11.8 SP1 Tutorial
- Design Files [ RAR, 315 MB ]
4.64 MB
09/2017
White Paper
Design Resources
Design Software Kits & Boards Power Analysis Programming & Debug IP cores Partners
BSDL Models IBIS Models Software User's Guides Design Resources Archives
FPGA Design Software
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FPGA Development Kits and Boards
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Power Analysis
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Programming and Debug
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IP Cores
Partners
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BSDL Models
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IBIS Models
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Software User Guides
| IGLOO2 Standalone Peripheral Initialization User Guide | User Guide | 2.5 MB | 9/2014 |
| SmartFusion2/IGLOO2 FPGA Timing Constraints User's Guide | User Guide | 4.24 MB | 9/2014 |
| Batch Flow TCL for SmartFusion2 and IGLOO2 | User Guide | 1.5 MB | 9/2014 |
| IGLOO2 System Builder Port/BIF Name Changes | User Guide | 360 KB | 12/2013 |
| IGLOO2 System Builder User Guide | User Guide | 3/2016 | |
| SmartFusion2 and IGLOO2 Block Flow Users Guide | User Guide | 244 KB | 12/2013 |
| SmartFusion2 and IGLOO2 Tcl for SoC Documentation | User Guide | 868 KB | 4/2015 |
Product Selector Guide
IGLOO2 FPGAs deliver more resources in low-density devices with low power requirements, proven security, and exceptional reliability. IGLOO2 FPGAs offer 5K-150K LEs with a high performance memory subsystem, up to 512KB embedded flash, 2 x 32 KB embedded static random-access memory (SRAM), two direct memory access (DMA) engines and two double data rate (DDR) controllers. These devices are ideal for general purpose functions such as Gigabit Ethernet or dual-PCI Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management, and secure connectivity.
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