ZL30415
OC-12 STM4 SONET/SDH Clock Multiplier Analog PLL
NOT RECOMMENDED FOR NEW DESIGNS
Overview
The ZL30415 is an analog phase locked loop (APLL) that performs jitter attenuation and rate conversion for SONET (synchronous optical network) and SDH (synchronous digital hierarchy) equipment. The APLL is specifically designed to meet the features, performance and price requirements of high-volume OC-3/STM-1 and OC-12/STM-4 line cards applications.
Features & Benefits
- Ultra low jitter generation of 4psRMS (40pspk-pk) maximum.
- Surpasses Telcordia GR-253-CORE jitter requirements for OC-3 and OC-12.
- Surpasses ITU-T G.813 jitter requirements for STM-1 and STM-4 rates.
- Easily accommodates the most stringent jitter requirements imposed by SONET/SDH devices.
- Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 MHz or 77.76 MHz
- Provides one differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz or 622.08 MHz.
- Provides a single-ended CMOS output clock at 19.44 MHz
- Provides a LOCK indication
- 3.3 V supply
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