White Paper
Documents
Document Name | Size | Published | Modified | |
---|---|---|---|---|
Improving ADC Results White Paper | 465.15 kB | 02/09/2007 | 02/09/2007 | |
In Circuit FPGA Debug Challenges Solutions | 1.1 MB | 05/14/2014 | 05/14/2014 | |
In-Circuit FPGA Debug- Challenges and Solutions | 1.25 MB | 03/25/2014 | 03/25/2014 | |
Increasing Fault Tolerance in Safety Critical Systems by Using Diverse Design with Programmable Logi
High reliability systems have to work no matter what - and a common method of combating down time is to duplicate at least some of the vital circuitry, so that the system can detect any single type of failure mode (whether it occurs naturally or is caused maliciously). With this capability, a system could either switch between the duplicate circuits in the event of a failure, or behave in a different way that is appropriate when at least 1 failure is detected. This can, however, cause at least one concern – what if the fault was something that affected the redundant circuitry too? You could be switching between failing circuitry continually and never solving the problem. By implementing the redundant device based on a very different technology, with differing (or diverse) failure modes and fault conditions for the redundant circuitry, this possibility can be alleviated. This paper looks at "Design Diversity" or differences in Programmable Logic technologies from a single vendor and demonstrates that the technology used from one generation to the next is often revolutionary and has no bearing on old design techniques.
|
Unknown | 06/26/2013 | 06/26/2013 | |
Introduction to Implementing Design Security with Microsemi SmartFusion2 and IGLOO2 FPGAs | 833.64 kB | 12/04/2013 | 02/11/2014 | |
Introduction to the SmartFusion2 and IGLOO2 Security Model | 464.77 kB | 11/26/2013 | 12/16/2013 | |
Jitter and Phase Noise Analysis of Actel's eX Devices | 2.17 MB | 05/29/2003 | 05/29/2003 | |
Live at Power-Up White Paper | 689.79 kB | 08/17/2005 | 08/17/2005 | |
Measurement of Worst Case Execution Time on PolarFire® SoC FPGA
Measurement of Worst Case Execution Time on PolarFire® SoC FPGA
|
137.79 kB | 10/04/2021 | 10/04/2021 | |
Microsemi Motor Control Solutions White Paper | 741.33 kB | 06/16/2014 | 06/16/2014 | |
Microsemi Secure Boot Reference Design White Paper | 1.52 MB | 03/10/2014 | 03/12/2014 | |
Migrating Motor Controller C++ Software to a PolarFire FPGA with Smart HLS Whitepaper | Unknown | 01/04/2021 | 08/17/2021 | |
Motor PowerFactor WP | 718.43 kB | 05/08/2013 | 05/08/2013 | |
Overview of Data Security Using Microsemi FPGAs and SoC FPGAs | 812.42 kB | 12/09/2013 | 12/15/2013 | |
Overview of Design Security Using Microsemi FPGAs and SoC FPGAs | 612.22 kB | 12/04/2013 | 02/11/2014 | |
Overview of Microsemi Antifuse Device Security | 344.8 kB | 12/04/2013 | 02/11/2014 | |
Overview of Secure Boot with Microsemi IGLOO2 FPGAs | 887.6 kB | 12/04/2013 | 02/11/2014 | |
Overview of Secure Boot with Microsemi SmartFusion2 FPGAs | 1.03 MB | 12/09/2013 | 12/15/2013 | |
Overview of Supply Chain Assurance of Intelligent ICs | 412.04 kB | 12/04/2013 | 02/11/2014 | |
PolarFire FPGA White Paper | 1.06 MB | 02/26/2018 | 03/06/2018 |