ZL30108
SONET/SDH Network Interface DPLL
Overview
| The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards. |
Simplified Block Diagram
Typical Applications
- Line card synchronization for SONET/SDH systems
Features & Benefits
- Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
- Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
- Provides a 19.44 MHz (SONET/SDH) clock output
- Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
- Provides automatic entry into Holdover and return from Holdover
- Hitless reference switching
- Provides lock and accurate reference fail indication
- Loop filter bandwidth of 29 Hz or 14 Hz
- Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
- Ultra Compact (5 mm x 5 mm) 32-pin QFN package
Resources
Documentation
Application Notes
- ZLAN-68 - List of Oscillators & Crystals that can be used with Zarlink's PLL, Digital Switches with Embedded PLL & Timing over Packet Devices
- ZLAN-178 - Synchronizer Power Supply Decoupling and Layout Practices
Product Previews
Downloads, Firmware and Drivers
- IBIS Models:
- zl30108lda.ibs
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Ordering
SONET/SDH Network Interface DPLL 32-Pin QFN EP Tray
| Distributor | SKU | Stock | MOQ | Pkg | |
|---|---|---|---|---|---|
| Microchip Technology Inc. | .. | .. | .. | .. | Buy Now |
| DigiKey | ZL30108LDG1-ND | 490 | Tray | No Stock |
