RISC-V Instruction Set Architecture
Microsemi recently announced it is the first FPGA provider to offer a comprehensive software tool chain and IP core for RISC-V designs. The company's RV32IM RISC-V core is available for Microsemi's IGLOO2 FPGAs, SmartFusion2 SoC FPGAs or RTG4 FPGAs, with an Eclipse-based SoftConsole IDE hosted on a Linux platform and the Libero SoC Design Suite providing full design support.
RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that is now a standard open architecture under the governance of the RISC-V Foundation. RISC-V is designed to be scalable for a wide variety of applications, easy to implement with regard to size and power, and offered under a permissive Berkeley Software Distribution (BSD) open source license. Through Microsemi's early involvement in the creation of the RISC-V Foundation, Microsemi has an established leadership role in the ecosystem.
SoftConsole IDE Downloads and Release Notes
- RISC-V Hardware Abstraction Layer
- RISC-V Bare Metal Boot Loader
- Other resources for RISC-V
- SmartFusion2 Security Evaluation Kit
- SmartFusion2 Advanced Development Kit
- SmartFusion2 Creative Board
For more information on RISC-V and the RISC-V Foundation, visit https://riscv.org/.
3rd party RISC-V solutions are also available from Microsemi partners: