RISC-V CPUs
Overview
Open. Lowest Power. Programmable RISC-V Solutions.
Microsemi offers a comprehensive suite of software tool chains and IP cores for your FPGA designs. The company's Mi-V RV32 RISC-V cores are available for Microsemi's PolarFire, RTG4, and IGLOO2 FPGAs. The Libero SoC (and Libero SoC PolarFire) Design suite provide complete support for FPGA designs and the Eclipse-based SoftConsole IDE provide a development environment, GCC compiler, debugger needed for C/C++ embedded firmware development.
The Libero SoC and SoftConsole development environments together provide all the required tools to port RISC-V Soft CPUs on Microsemi's FPGA portfolio and develop, test and debug embedded firmware.
To get started with your first RISC-V based development on Microsemi's FPGAs follow the sections below.
- Getting Started - Step by step instructions to run and modify sample projects and port them on Microsemi's FPGAs.
- Design Your Own - Introduces how to modify the RISC-V reference design and add peripherals or other logic in the FPGA
RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that is now a standard open architecture under the governance of the RISC-V Foundation. RISC-V is designed to be scalable for a wide variety of applications, easy to implement with regard to size and power, and offered under a permissive Berkeley Software Distribution (BSD) open source license. Through Microsemi's early involvement in the creation of the RISC-V Foundation, Microsemi has an established leadership role in the ecosystem.
Getting Started
Getting Started with RISC-V
This page provides the step-by-step instructions to program the target FPGA board with a RISC-V Soft CPU, program an example project on the Soft CPU using SoftConsole and Running the firmware.
This example uses the IGLOO2 Creative Development Board, but these same steps apply to any of the FPGA and its corresponding evaluation board.
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Design Your Own
Design your Own RISC-V Subsystem on FPGA
This page provides the high level instructions to port your first RISC-V Soft CPU on a Microsemi FPGA and download your custom embedded firmware on the hardware. Detailed step-by-step instructions are available in the Building a RISC-V Processor Subsystem Tutorial.
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In order to port your own RISC-V subsystem on a Microsemi FPGA, you will need to use Libero SoC or Libero SoC PolarFire to create an FPGA design using the RISC-V processor core and other IP peripherals to build the subsytem. You will configure and connect the IPs and run the design to create a programming file for the target hardware. Then use SoftConsole to develop and build the user application that tuns on the target device. |
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CPU Cores
| RISC-V Soft CPU | LE'S | CoreMark Score | Cache Size | Mul/Div | Floating Point | Availability |
| CORE_RISCV_AXI4* | 10K | 2.01 | 8K I and D | Yes | N/A | Now |
| Mi_V_RV32IMAF_L1_AHB* | 26K | 2.01 | 8K I and D | Yes | Single Precision | Now |
| Mi_V_RV32IMA_L1_AHB* | 10K | 2.01 | 8K I and D | Yes | N/A | Now |
| Mi_V_RV32IMA_L1_AXI* | 10K | 2.01 | 8K I and D | Yes | N/A | Now |
*Click the RISC-V Soft CPU to download the Handbook
- Additional cores can be added based on customer demand
