Mi-V RISC-V Ecosystem

Overview

Open. Lowest Power. Programmable RISC-V Solutions.

The Mi-V™ RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microsemi and numerous third parties to fully support RISC-V designs. The Mi-V™ ecosystem aims to increase adoption of RISC-V ISA and Microsemi's
soft CPU product family.

There are 6 main categories that make up the Mi-V RISC-V ecosystem:

RISC-V CPUs:

Jumpstart your RISC-V designs with Microsemi's comprehensive suite of RISC-V Soft IP Cores. Mircosemi's RISC-V IP cores are readily available for RTG4, IGLOO2 and PolarFire FPGAs.

Microsemi introduces the industry's first RISC-V SoC FPGA Architecture, PolarFire SoC. PolarFire SoC brings deterministic real-time performance to Linux in a coherent multi-core RISC-V CPU.

Design Tools:

Mi-V Ecosystem consists of various design tools such as the Libero SoC FPGA Design Suite, Eclipse based IDE SoftConsole enabling quick C and C++ development, a Firmware Catalog consisting of numerous drivers, and third party platforms for development, simulation and debug.

Boards:

Accelerate your time to market with our comprehensive series of full-featured and low-cost development boards that run RISC-V Soft IP cores out of the box.

Operating Systems:

Microsemi, along with partners, supports the most popular commercial and open-source operating systems and RTOS for RISC-V implementations on FPGA.

Solutions:

A collection of example projects, drivers and firmware running on RISC-V implementations that can accelerate your design cycle.

Design Support:

Microsemi is dedicated to provide excellent customer support ranging from online technical support to training. A collation of various support services available from Microsemi are listed here.

Renode Webinar Series

Getting Started with the RISC-V Based PolarFire™ SoC FPGA Webinar Series

Learn how to get started with the PolarFire SoC FPGA, the world’s first RISC-V based SoC FPGA, to create fully deterministic, real-time systems alongside the Linux® operating system. We are holding a series of webinars to introduce you to the free Renode™ development platform from Mi-V partner Antmicro that is available with our SoftConsole v6.0 software development environment. You will see demo applications, learn how to create projects, and find out how to set up and configure your own systems targeting the new SoC FPGA architecture.

Click here to register.

Webinar 1 (May 2): Discover Renode for PolarFire™ SoC Design and Debug

In this introductory session, we will provide you with an overview of SoftConsole 6.0 with Renode™ integration. We will introduce you to the Renode development framework and provide an overview of the platform and its features. You will also learn about the PolarFire™ SoC architecture and how to use Renode to develop your application. View the Recording

Agenda
Introduction to the PolarFire SoC
What Renode is
What Renode isn’t
Benefits of Renode

Webinar 2 (June 6): How to Get Started with Renode for PolarFire SoC

In Session 2, we will show you how to get started with the Renode development platform. We’ll walk through the installation of SoftConsole 6.0 on the Windows® operating system, as well as several flavors of the Linux® operating system, and discuss how to resolve any installation issues. Once the installation is complete, you will learn how to launch and run the included demo programs and verify your SoftConsole 6.0 installation and Renode set up.

Agenda
How to install Renode on all platforms Troubleshooting installation problems
How to use Renode: Introduction to existing model and initial setup

Webinar 3 (July 4): Learn to Debug a Bare-Metal PolarFire SoC Application with Renode

In Session 3, we will show you the pse-blinky demo example that emulates a PolarFire™ SoC system in the Renode development platform with five available harts. You’ll learn how to configure the debug session and how to connect to the hart. We will demonstrate the configuration of the UART analyzer and individual peripherals, then run the example project and simultaneously debug on multiple harts in separate debug sessions.

Agenda
Running “hello world” on each core Using UARTS
Using timers
Demo of execution from eNVM Run and show a debug session

Webinar 4 (Aug. 1): Tips and Tricks for Even Easier PolarFire SoC Debug with Renode

In Session 4, we will recap what has been covered in previous sessions and answer questions that have been raised after each session. We will then demonstrate common Renode™ commands and command syntax and provide an explanation and example of available logging levels. You’ll also learn how to configure SoftConsole launch groups and how to create and use macros for Renode. We will also discuss the primary differences between Renode and Silicon.

Agenda
Common Renode commands
Showcase logging levels
Making launchers
Making macros Renode vs. Silicon

Webinar 5 (Sept. 5): Add and Debug PolarFire SoC Peripherals with Renode

In Session 5 you will learn how to add local memory to a Renode system and execute code. From there, we’ll cover the creation and addition of a timer to the system to create interrupts. A GPIO will then be added, followed by the set up and configuration of MonoDevelop, which is used to create peripherals for Renode. We’ll then create a custom UART that will be added to the system to be compiled just in time.

Agenda
Creating local memory in fabric
Adding a timer on fabric and generate and handle an interrupt
Adding GPIO to fabric
Setting up Mono develop
Creating custom UART and adding it just-in-time to platform

Webinar 6 (Oct. 3): Intro to PolarFire SoC MSS Configuration and Software Flow

In Session 6, we will cover the embedded software development flow for the PolarFire™ SoC. We will describe the hardware-level configuration for the microprocessor subsystem, memory configuration, logical separation for security and boot processes and how they integrate into a classic embedded software development flow.

Agenda
MSS configuration and deployment
Memory configuration
L2 cache
TIM Logical separation: PMP configuration
Boot process: E51 services

Mi-V Partners

Mi-V RISC-V Partners

		Amazon FreeRTOS is open source and extends the FreeRTOS kernel with libraries making it easy to connect to cloud services and edge devices. Amazon FreeRTOS support is now available for RISC-V based MCUs.
		Antmicro’s Renode Simulation platform offers multiple connected virtual device setups within the same environment enabling ease of development for customers without the hassle of C programming.
		ARIES Embedded offers hardware products (modular systems and custom designs), services for IP-development and software development (FreeRTOS, U-Boot, Linux) based on Microsemi's Polarfire FPGA and SoCs.
		Digital Core Technologies offers design services covering the entire Life Cycle of a product. This includes Hardware Designs (High Speed, High-Density Digital, Analog, Power and RF), Embedded Logic Ware and Embedded Software
		DornerWorks specializes in FPGA Design and Engineering, Embedded Software and Hardware Development. Their expertise includes designs for the Aerospace, Medical, Automotive and IoT markets.
		Emcraft is a leading provider of System-on-Module (SoM) solutions. They provide production-ready, self-maintained Linux BSPs and Software distributions for all of their SoM Solutions.
		Emdalo Technologies a software engineering development company specializing in delivering solutions in Embedded Systems, Machine Learning, AI, Information Security and IIoT Applications.
		Express Logic provides comprehensive X-WARE IoT Platform for embedded developers targeting FPGAs. The THREADX RTOS has been ported to the RISC-V Soft CPU on the PolarFire MPF300-EVAL-KIT evaluation board.
		Hex Five Security, Inc. is the creator of MultiZone™ Security, the first trusted execution environment for RISC-V, which provides policy-based hardware-enforced separation for an unlimited number of security domains, with full control over data, code, peripherals and interrupts.
		IAR Embedded Workbench is an integrated development environment for building and debugging embedded applications using C and C++. The toolchain offers leading code quality, size and speed; extensive debug with simulator and hardware debugging support.
		Imperas supports Microsemi's RISC-V based SoC FPGAs with the Mi-V FreeRTOS Extendable Platform Kit (EPK), tools to help in development, porting, debug and test.
		Micrium provides high-quality embedded software components in the form of engineer-friendly source code coupled with unsurpassed documentation and customer support.
		Phytec is a leading provider of SoM solutions based on application processors and FPGAs. Phytec also offers services: systems integration, hardware and software design, mechanical design and manufacturing.
		SecureRF provides security solutions for embedded systems and wireless sensor technologies. SecureRF is a CompanionCore partner of Microsemi and offers optimized IP cores for Microsemi FPGAs.
		SiFive builds customized silicon based on the open-source RISC-V ISA. SiFive offers customizable RISC-V CPU Core IP for use in Microsemi FPGAs reducing time-to-market and cost.
		Technolution provides tailor-made solutions such as Fault Tolerant RISC-V soft cores, High speed Interfaces, BSP and Drivers, Real-time Video transport, and High-end Board design.
		VectorBlox is an IP licensing and design services firm specializing in FPGA-based computing solutions. They offer FPGA-optimized RISC-V cores, a massively parallel accelerator, the MXP Matrix Processor, and design services.
		The Zephyr Project is an open source collaborative effort to build a small, scalable RTOS. Zephyr OS has been ported on the Mi-V RISC-V Soft CPU deployed on the IGLOO2 FPGA on the Evaluation Kit M2GL-EVAL-KIT.