Mi-V RISC-V Ecosystem
Overview
Open. Lowest Power. Programmable RISC-V Solutions.
The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microsemi and numerous third parties to fully support RISC-V designs. The Mi-V ecosystem aims to increase adoption of RISC-V ISA and Microsemi's soft CPU product family.
PolarFire SoC
Learn more about the industry's first RISC-V SoC FPGA Architecture.
RISC-V Soft CPU
Microsemi offers a comprehensive suite of software tool chains and IP cores for your FPGA designs. The Mi-V RV32 RISC-V cores are available for Microsemi's PolarFire, RTG4, and IGLOO2 FPGAs. The Libero SoC Design suite provide complete support for FPGA designs and the Eclipse-based SoftConsole IDE provide a development environment, GCC compiler, and debugger needed for C/C++ embedded firmware development.
The Libero SoC and SoftConsole development environments together provide all the required tools to port RISC-V Soft CPUs on Microsemi's FPGA portfolio and develop, test and debug embedded firmware.
| RISC-V Soft CPU | Mi-V_RV32IMAF_L1_AHB | Mi-V_RV32IMA_L1_AHB | Mi-V_RV32IMA_L1_AXI | Mi-V_RV32IMC |
|---|---|---|---|---|
| LEs | 26k | 10k | 10k | 4k-10k |
| Coremark Score | 2.01 | 2.01 | 2.01 | 0.17-2.77 |
| Cache Size | 8K I/D | 8K I/D | 8K I/D | N/A |
| Tightly Coupled Memory (TCM) | N/A | N/A | N/A | Yes- configurable depth |
| Compressed | N/A | N/A | N/A | Optional |
| Mul/Div | Yes | Yes | Yes | Optional-MACC Pipelined-MACC or 32 cycle fabric |
| Atomics | Yes | Yes | Yes | N/A |
| Floating Point | Single Precision | N/A | N/A | N/A |
| Interface(s) | AHB | AHB | AXI | APB3/AHB/AXI |
| Interrupts | 31 External Soft Timer | 31 External Soft Timer | 31 External Soft Timer | External Soft Timer ECC up to 6 configurable Vectored Mode |
| Debug | Yes | Yes | Yes | Optional |
| ECC | Optional | Optional | N/A | Optional |
| Availability | Now | Now | Now | Now |
Getting Started
Step 1: Download and Install the Latest Tools
| Downloads | Description |
| Libero SoC Design Suite | Libero SoC design suite is a comprehensive tool for designing with Microsemi FPGAs and SoCs |
| SoftConsole | SoftConsole is a free software development environment for embedded firmware development |
Step 2: Choose a Target to view the compatible reference material
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PolarFire Evaluation Kit
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PolarFire Splash Kit
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RTG4 Development Kit
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Mi-V Creative Board
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Renode
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The PolarFire Evaluation kit is a full-featured kit that offers evaluation of high-speed transceivers, 10GbE, IEEE1588, JESD204B, SyncE, CPRI and more. The kit includes an HPC FMC, PCIe, dual GbE, SFP+ and USB. Price: $1500.
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Step 3: Download the reference material compatible with your target
PolarFire Evaluation Kit |
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| Reference Material | Description |
| TU0775: How to build a Mi-V soft CPU subsystem TU0775: Design file |
A complete user guide to build a basic Mi-V CPU subsystem and execute a first embedded application |
| Mi-V_RV32IMA_L1_AHB Handbook Mi-V_RV32IMA_L1_AXI Handbook Mi-V_RV32IMAF_L1_AHB Handbook |
Handbooks for Mi-V Soft CPUs |
| AC466: Application Note AC466: Design Files |
A guide to implement Auto update and In-Application Programming using a Mi-V Soft-CPU |
| DG0798: Demo Guide DG0798: Design Files |
A guide to access the PolarFire FPGA System Services using a Mi-V Soft-CPU |
| DG0799: Demo Guide DG0799: Design Files |
A guide to run a 1G Ethernet Loopback design using IOD CDR, CoreTSE and a Mi-V Soft-CPU |
| DG0802: Demo Guide DG0802: Design Files |
A guide to implement, control and communicate using a PCIe Root port using a Mi-V Soft-CPU |
| RISC-V ISA Specification RISC-V ISA Privileged Specification RISC-V Debug Specification |
RISC-V Specification Documentation |
| Target: MPF300-EVAL-KIT | Complete kit information - ordering, documentation, support etc. |
Documents
Tutorials
| Tutorials | Description |
| TU0775: Mi-V Soft-CPU Tutorial (PolarFire) TU0775: Design Files |
A complete user guide to build a basic Mi-V CPU subsystem and execute a first embedded application in a PolarFire FPGA |
| AC490: RTG4 FPGA: Building a Mi-V Processor Subsystem | A complete user guide to build a basic Mi-V CPU subsystem and execute a first embedded application in RTG4 FPGA |
Application Notes
| Application Notes | Description |
| AC464: Security Application note AC464: Design Files |
A guide to interface the crypto co-processor with a Mi-V Soft-CPU and implement data security |
| AC466: Application note AC466: Design Files |
A guide to implement auto-update and In-Application Programming using a Mi-V Soft-CPU |
Demo Guides
| Demo Guides | Description |
| DG0798: Demo Guide DG0798: Design Files |
A guide to access the PolarFire FPGA system services using a Mi-V Soft-CPU |
| DG0799: Demo Guide DG0799: Design Files |
A guide to run a 1G Ethernet Loopback design using IOD CDR, CoreTSE and a Mi-V Soft-CPU |
| DG0802: Demo Guide DG0802: Design Files |
A guide to implement, control and communicate using a PCIe Root port using a Mi-V Soft-CPU |
Soft-CPU Documentation
| Soft-CPU | Document |
| Mi-V_RV32IMA_L1_AHB | Handbook |
| Mi-V_RV32IMA_L1_AXI | Handbook |
| Mi-V_RV32IMAF_L1_AHB | Handbook |
RISC-V Specification
| RISC-V Reference Material | Description |
| ISA Spec | RISC-V ISA Specification Document |
| Privileged ISA Spec | RISC-V Privileged ISA Specification Document |
| Debug Spec | RISC-V ISA Debug Specification Document |
Software Documentation
| Software Documentation | Description |
| Libero SoC | Libero SoC Documentation |
| SoftConsole | SoftConsole Documentation |
| Renode Installation | SoftConsole v6.0 Release Notes |
| Renode Documentation | Complete Renode Documentation |
Renode Webinar Series
Getting Started with the RISC-V Based PolarFire SoC FPGA Webinar Series
Learn how to get started with the PolarFire SoC FPGA, the world’s first RISC-V based SoC FPGA, to create fully deterministic, real-time systems alongside the Linux® operating system. We are holding a series of webinars to introduce you to the free Renode™ development platform from Mi-V partner Antmicro that is available with our SoftConsole v6.2 software development environment. You will see demo applications, learn how to create projects, and find out how to set up and configure your own systems targeting the new SoC FPGA architecture.
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Click here to register for the webinar series!
Webinar 1 (May 2, 2019): Discover Renode for PolarFire SoC Design and Debug
In this introductory session, we will provide you with an overview of SoftConsole 6.0 with Renode™ integration. We will introduce you to the Renode development framework and provide an overview of the platform and its features. You will also learn about the PolarFire™ SoC architecture and how to use Renode to develop your application.
Agenda
Introduction to the PolarFire SoC
What Renode is
What Renode isn’t
Benefits of Renode
View the Recording
Download the Presentation
Webinar 2 (June 6, 2019): How to Get Started with Renode for PolarFire SoC
In Session 2, we will show you how to get started with the Renode development platform. We’ll walk through the installation of SoftConsole 6.0 on the Windows® operating system, as well as several flavors of the Linux® operating system, and discuss how to resolve any installation issues. Once the installation is complete, you will learn how to launch and run the included demo programs and verify your SoftConsole 6.0 installation and Renode set up.
Agenda
How to install Renode on all platforms Troubleshooting installation problems
How to use Renode: Introduction to existing model and initial setup
Installation videos for SoftConsole v6.0 on various operating systems:
View the Recording
Download the Presentation
Webinar 3 (July 4, 2019): Learn to Debug a Bare Metal PolarFire SoC Application with Renode
In Session 3, we will show you the pse-blinky demo example that emulates a PolarFire™ SoC system in the Renode development platform with five available harts. You’ll learn how to configure the debug session and how to connect to the hart. We will demonstrate the configuration of the UART analyzer and individual peripherals, then run the example project and simultaneously debug on multiple harts in separate debug sessions.
Agenda
Running “hello world” on each core Using UARTS
Using timers
Demo of execution from eNVM Run and show a debug session
View the Recording
Download the Presentation
Webinar 4 (Aug. 1, 2019): Tips and Tricks for Even Easier PolarFire SoC Debug with Renode
In Session 4, we will recap what has been covered in previous sessions and answer questions that have been raised after each session. We will then demonstrate common Renode™ commands and command syntax and provide an explanation and example of available logging levels. You’ll also learn how to configure SoftConsole launch groups and how to create and use macros for Renode. We will also discuss the primary differences between Renode and Silicon.
Agenda
Common Renode commands
Showcase logging levels
Making launchers
Making macros Renode vs. Silicon
View the Recording
Download the Presentation
Webinar 5 (Sept. 5, 2019): Add and Debug PolarFire SoC Peripherals with Renode
In Session 5 you will learn how to add local memory to a Renode system and execute code. From there, we’ll cover the creation and addition of a timer to the system to create interrupts. A GPIO will then be added, followed by the set up and configuration of MonoDevelop, which is used to create peripherals for Renode. We’ll then create a custom UART that will be added to the system to be compiled just in time.
Agenda
Creating local memory in fabric
Adding a timer on fabric and generate and handle an interrupt
Adding GPIO to fabric
View the Recording
Download the Presentation
Webinar 6 (Oct. 3, 2019): Add and Debug a Pre-existing Peripheral in PolarFire SoC
In Session 6, you will learn to edit the PolarFire SoC fabric configuration to add a UART and build and debug the Renode Emulation Platform in the Mono Develop IDE using Linux.
Agenda
Add a UART to the fabric
Building Renode from source
Debugging a model
Supporting Video
View the Recording
Download the Presentation
Webinar 7 (Nov. 7, 2019): Create Custom Models - Filters, Offloading, Acceleration
In this webinar you will learn how to create a custom peripheral from start to finish, compile and build it in the Renode platform.
Agenda
Creating a peripheral model
Adding the model to the Renode platform
Building the peripheral with the Renode platform
View the Recording
Download the Presentation
Webinar 8 (Dec. 5, 2019): What's New in SoftConsole v6.2
This webinar will cover the new features released in SoftConsole v6.2 and the changes to Renode configuration and set up.
Agenda
Getting Started with Libero SoC v12.3
Using Renode for PolarFire SoC Designs
View the Recording
Download the Presentation
Webinar 9 (Jan. 9, 2020): Getting Started with the Libero® SoC Design Suite v12.3 and Renode
In this webinar we show you the latest Libero tools release with support for the PolarFire® SoC FPGA family using an Early Access Program (EAP) license. We will use the Libero tools to create a simple PolarFire SoC FPGA design using the RISC-V microprocessor subsystem, implement the processor set up in Renode, and then test using SoftConsole.
View the Recording
Download the Presentation
Webinar 10 (Feb. 13, 2020): Introduction to the MPFS Bare Metal Library
In this webinar the MPFS Bare Metal Library will be introduced and its features explained. You will be shown where to locate and clone the Bare Metal Library and how to use it in your development.
Agenda
What is the MPFS Bare Metal Library
Downloading the Bare Metal Library
Using the Bare Metal Library in your project
View the Recording
Download the Presentation
Webinar 11 (Mar. 12, 2020): Handling Binaries
This session will show you how one binary is used by all of the cores in the PF SoC system and how it is built
Agenda
Overview of binaries
Building the executable
Running the application
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Webinar 12 (Apr. 9, 2020): Using a Simple Peripheral as Software Stimulus
Here a model of an I2C current and voltage sensor will be demonstrated. The model will produce varying sensor values as software stimulus for testing.
Agenda
I2C model and functionality
Adding the model using JIT
Accessing the model from software
View the Recording
Download the Presentation
Webinar 13 (May 14, 2020): Two Bare Metal Applications on PolarFire SoC
In this webinar you will learn how to configure the PolarFire SoC system to run two distinct applications on separate harts using memory protection (PMP), expanded memory (LIM), and coherent message sharing.
Agenda
Configuring the PolarFire SoC system
Configuring the software
Running software on the system
Debugging the system
Register
Webinar 14 (June 11, 2020): The PolarFire SoC Icicle Kit Model on Renode
This webinar will introduce the PolarFire SoC Icicle Kit Model using Renode and SoftConsole and demonstrate its features.
Agenda
PolarFire SoC Icicle Kit Overview
Demonstration of the Icicle Kit Model on Renode
Register
Webinar 15 (July 9, 2020): Linux on PolarFire SoC
This webinar will introduce the process for building Linux for use on PolarFire SoC and running it on Renode.
Agenda
Building Linux
Register
Webinar 16 (August 13, 2020): Build Applications for Linux on PolarFire SoC
This webinar will show you how to create a Linux application for PolarFire SoC and test them on the Renode emulation platform.
Agenda
Creating a Linux application
Building the application
Testing the application on Renode
Register
Webinar 17 (September 10, 2020): AMP Mode
In this webinar the Asymmetric Multi Processing mode (AMP) for PolarFire SoC applications will be explained and its use demonstrated
Agenda
What is AMP
AMP configuration
Register
Mi-V Partners
Articles and News
12/18/2019 - EE Journal:Microchip PolarFire Takes a RISC (-V)
12/14/2019 - ServeTheHome: Key Takeaways from the 2019 RISC-V Summit
12/11/2019 - VentureBeat:RISC-V grows globally as an alternative to Arm and its license fees
12/11/2019 - Phoronix: Microchip announces PolarFire SoC : FPGA fabirc with integrated RISC-V cores
12/11/2019 - eeNews Embedded:Early-access program for RISC-V enabled PolarFire SoC family
12/11/2019 - CNX Software:RISC-V based PolarFire SoC FPGA and Devkit Coming in Q3 2020
12/11/2019 - ThomasNet: Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC Family
12/11/2019 - New Electronics:Microchip opens Early Access Program for the PolarFire system-on-chip FPGA
12/10/2019 - LinuxGizmos.com: Andes' RISC-V SoC debuts with AI-ready VPU as Microchip opens access to its PolarFire SoC
12/10/2019 - Electronic Design:Microchip Delivers RISC-V Hard-Core FPGA SoCs
12/10/2019 - All About Circuits:Microchip Announces First RISC-V-based SoC FPGA to Use Half the Power of Other FPGAs
12/10/2019 - Microchip:Microchip Unveils Family Details and Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC FPGA Family
05/22/2019 - IAR Systems: IAR Systems Takes RISC-V to the Next Level with Launch of Professional Development Tools
05/03/2019 - EE Times: Spacecraft Communications Call for Sophisticated Data-Transmission Techniques
04/29/2019 - Electronics 360: 4 Reasons to use RISC-V for aerospace and defense applications
04/20/2019 - Design News: 8 RISC-V Companies to Watch
03/26/2019 - All About Circuits: Running Hard Real-Time Applications and Linux on PolarFire SoC
02/26/2019 - UltraSoC: UltraSoC demonstrates advanced multicore debug at Embedded World 2019
02/14/2019 - EBN: Open Source Hardware Benefits Procurement Practices
02/01/2019 - Aerospace & Defense: Using RISC-V to Simplify Data Logging in Space
12/04/2018 - LinuxGizmos.com: World’s first RISC-V-based FPGA SoC runs Linux
12/04/2018 - New Electronics: Microchip unveils new class of SoC FPGA
12/04/2018 - ElectronicsWeekly: Microsemi adds to RISC-V based FPGAs
12/04/2018 - EE Times: RISC-V Takes a Leap Forward
12/04/2018 - Microchip: Industry's First RISC-V SoC FPGA Architecture Brings Real-Time to Linux, Giving Developers the Freedom to Innovate in Low-Power, Secure and Reliable Designs
09/10/2018 - RISC-V Foundation: RISC-V Fall Newsletter 2018
06/05/2018 - RISC-V Foundation: RISC-V Summer Newsletter 2018
05/07/2018 - Microchip: Microsemi and SiFive Launch HiFive Unleashed Expansion Board, Enabling Linux Software and Firmware Developers to Build RISC-V PCs for the First Time
04/17/2018 - Microchip: Microsemi's Mi-V Ecosystem Continues to Expand as New Member Antmicro Joins to Develop Mi-V RISC-V Processor Subsystems for PolarFire FPGAs
04/05/2018 - SatMagazine: Improving Space Systems Designs Using FPGAs with RISC-V Cores
03/26/2018 - Embedded Systems Engineering: Plugging Security Vulnerabilities in Servers and Data Center Architectures
02/26/2018 - Semiconductor Engineering: RISC-V Gains Its Footing
02/23/2018 - RISC-V Foundation: RISC-V Winter Newsletter 2018
02/15/2018 - ExpressLogic: Express Logic’s X-Ware IoT Platform® Brings Industrial-Grade IoT Support to RISC-V Architecture
02/13/2018 - ExpressLogic: Express Logic, Inc. announces that its industrial-grade X-Ware IoT Platform®—powered by the industry-leading ThreadX® RTOS—provides turnkey support for Microsemi’s Mi-V RISC-V instruction set architectures (ISAs)
02/13/2018 - Military Embedded Systems: Using RISC-V in FPGAs for strategic defense systems
01/31/2018 - Electronic Design: 11 Myths About the RISC-V ISA
10/20/2017 - RISC-V Foundation: RISC-V E-Newsletter October 2017
10/19/2017 - Microsemi: Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V
06/18/2017 - Embedded Computing Design: Growing the pie: Eclipse-based Windows IDE gives more access to RISC-V developers
06/16/2017 - Elektronik Praxis: SoftConsole 5.1: Windows Eclipse IDE with support for RISC-V command sets
06/16/2017 - New Electronics: Microsemi launches Windows-based RISC-V IDE
06/15/2017 - Microsemi: Microsemi Announces SoftConsole v5.1, the World's First Freely Available Windows-Hosted Eclipse Integrated Development Environment Supporting RISC-V Open Instruction Set Architecture
06/15/2017 - Tech Design Forum: Microsemi builds Windows IDE for RISC-V
06/15/2017 - Markt & Technik: Free Windows IDE for RISC-V
06/15/2017 - Radio-electronics.com: Microsemi Announces SoftConsole v5.1, for Windows
06/15/2017 - Electronic Specifier: IDE showcased at Design Automation Conference in Texas
11/16/2016 - Microsemi: Microsemi is First FPGA Provider to Offer Open Architecture RISC-V IP Core and Comprehensive Software Solution for Embedded Systems
