Mi-V RISC-V Ecosystem

Overview

Open. Lowest Power. Programmable RISC-V Solutions.

The Mi-V RISC-V ecosystem is a continuously expanding, comprehensive suite of tools and design resources developed by Microsemi and numerous third parties to fully support RISC-V designs. The Mi-V ecosystem aims to increase adoption of RISC-V ISA and Microsemi's soft CPU product family.

PolarFire SoC

Learn more about the industry's first RISC-V SoC FPGA Architecture.

RISC-V Soft CPU

Microsemi offers a comprehensive suite of software tool chains and IP cores for your FPGA designs. The Mi-V RV32 RISC-V cores are available for Microsemi's PolarFire, RTG4, and IGLOO2 FPGAs. The Libero SoC Design suite provide complete support for FPGA designs and the Eclipse-based SoftConsole IDE provide a development environment, GCC compiler, and debugger needed for C/C++ embedded firmware development.

The Libero SoC and SoftConsole development environments together provide all the required tools to port RISC-V Soft CPUs on Microsemi's FPGA portfolio and develop, test and debug embedded firmware.

RISC-V Soft CPU	LEs	Coremark Score	Cache Size	Mul/Div	Floating Point	Availability
Mi-V_RV32IMAF_L1_AHB	26k	2.01	8K I/D	Yes	Single Precision	Now
Mi-V_RV32IMA_L1_AHB	10k	2.01	8K I/D	Yes	N/A	Now
Mi-V_RV32IMA_L1_AXI	10k	2.01	8K I/D	Yes	N/A	Now

Getting Started

Step 1: Download and Install the Latest Tools

Downloads	Description
Libero SoC Design Suite	Libero SoC design suite is a comprehensive tool for designing with Microsemi FPGAs and SoCs
SoftConsole	SoftConsole is a free software development environment for embedded firmware development

Step 2: Choose a Target to view the compatible reference material

PolarFire Evaluation Kit	PolarFire Splash Kit	RTG4 Development Kit	Mi-V Creative Board	Renode

The PolarFire Evaluation kit is a full-featured kit that offers evaluation of high-speed transceivers, 10GbE, IEEE1588, JESD204B, SyncE, CPRI and more. The kit includes an HPC FMC, PCIe, dual GbE, SFP+ and USB. Price: $1500. The PolarFire Splash kit is a general-purpose kit that offers a platform for evaluation and development. The kit includes GbE, PCIe, USB and LPC FMC. Price: $699. The RTG4 Development kit provides aerospace customers with an evaluation platform for data transmission, serial connectivity, bus interface and high speed designs using Radiation-Tolerant High-Performance RTG4 FPGAs. Contact local sales for pricing information. The Future Electronics Mi-V Creative Development board is a low-cost evalution platform for hardware and software engineers using RISC-V soft CPUs on Microsemi IGLOO2 FPGA. Price: $149.95. Renode provides a simulation model of Mi-V soft-CPUs and can be used to debug firmware. Renode is bundled with SoftConsole and can be downloaded for free.

Step 3: Download the reference material compatible with your target

PolarFire Evaluation Kit
Reference Material	Description
TU0775: How to build a Mi-V soft CPU subsystem TU0775: Design Files	A complete user guide to build a basic Mi-V CPU subsystem and execute a first embedded application
Mi-V_RV32IMA_L1_AHB Handbook Mi-V_RV32IMA_L1_AXI Handbook Mi-V_RV32IMAF_L1_AHB Handbook	Handbooks for Mi-V Soft CPUs
AC464: Security Application Note AC464: Design Files	A guide to interface the crypto co-processor with a Mi-V Soft-CPU and implement data security
AC466: Application Note AC466: Design Files	A guide to implement Auto update and In-Application Programming using a Mi-V Soft-CPU
DG0798: Demo Guide DG0798: Design Files	A guide to access the PolarFire FPGA System Services using a Mi-V Soft-CPU
DG0799: Demo Guide DG0799: Design Files	A guide to run a 1G Ethernet Loopback design using IOD CDR, CoreTSE and a Mi-V Soft-CPU
DG0802: Demo Guide DG0802: Design Files	A guide to implement, control and communicate using a PCIe Root port using a Mi-V Soft-CPU
RISC-V ISA Specification RISC-V ISA Privileged Specification RISC-V Debug Specification	RISC-V Specification Documentation
Target: MPF300-EVAL-KIT	Complete kit information - ordering, documentation, support etc.

Documents

Tutorials

Tutorials	Description
TU0775: Mi-V Soft-CPU Tutorial (PolarFire) TU0775: Design Files	A complete user guide to build a basic Mi-V CPU subsystem and execute a first embedded application in a PolarFire FPGA
Mi-V Soft-CPU Tutorial (RTG4) Design Files (coming soon)	A complete user guide to build a basic Mi-V CPU subsystem and execute a first embedded application in RTG4 FPGA

Application Notes

Application Notes	Description
AC464: Security Application note AC464: Design Files	A guide to interface the crypto co-processor with a Mi-V Soft-CPU and implement data security
AC466: Application note AC466: Design Files	A guide to implement auto-update and In-Application Programming using a Mi-V Soft-CPU

Demo Guides

Demo Guides	Description
DG0798: Demo Guide DG0798: Design Files	A guide to access the PolarFire FPGA system services using a Mi-V Soft-CPU
DG0799: Demo Guide DG0799: Design Files	A guide to run a 1G Ethernet Loopback design using IOD CDR, CoreTSE and a Mi-V Soft-CPU
DG0802: Demo Guide DG0802: Design Files	A guide to implement, control and communicate using a PCIe Root port using a Mi-V Soft-CPU

Soft-CPU Documentation

Soft-CPU	Document
Mi-V_RV32IMA_L1_AHB	Handbook
Mi-V_RV32IMA_L1_AXI	Handbook
Mi-V_RV32IMAF_L1_AHB	Handbook

RISC-V Specification

RISC-V Reference Material	Description
ISA Spec	RISC-V ISA Specification Document
Privileged ISA Spec	RISC-V Privileged ISA Specification Document
Debug Spec	RISC-V ISA Debug Specification Document

Software Documentation

Software Documentation	Description
Libero SoC	Libero SoC Documentation
SoftConsole	SoftConsole Documentation
Renode Installation	SoftConsole v6.0 Release Notes
Renode Documentation	Complete Renode Documentation

Renode Webinar Series

Getting Started with the RISC-V Based PolarFire SoC FPGA Webinar Series

Learn how to get started with the PolarFire SoC FPGA, the world’s first RISC-V based SoC FPGA, to create fully deterministic, real-time systems alongside the Linux® operating system. We are holding a series of webinars to introduce you to the free Renode™ development platform from Mi-V partner Antmicro that is available with our SoftConsole v6.0 software development environment. You will see demo applications, learn how to create projects, and find out how to set up and configure your own systems targeting the new SoC FPGA architecture.

Click here to register.

Webinar 1 (May 2): Discover Renode for PolarFire SoC Design and Debug

In this introductory session, we will provide you with an overview of SoftConsole 6.0 with Renode™ integration. We will introduce you to the Renode development framework and provide an overview of the platform and its features. You will also learn about the PolarFire™ SoC architecture and how to use Renode to develop your application. View the Recording.

Agenda
Introduction to the PolarFire SoC
What Renode is
What Renode isn’t
Benefits of Renode

Webinar 2 (June 6): How to Get Started with Renode for PolarFire SoC

In Session 2, we will show you how to get started with the Renode development platform. We’ll walk through the installation of SoftConsole 6.0 on the Windows® operating system, as well as several flavors of the Linux® operating system, and discuss how to resolve any installation issues. Once the installation is complete, you will learn how to launch and run the included demo programs and verify your SoftConsole 6.0 installation and Renode set up. View the Recording.

Agenda
How to install Renode on all platforms Troubleshooting installation problems
How to use Renode: Introduction to existing model and initial setup

Installation videos for SoftConsole v6.0 on various operating systems:

Webinar 3 (July 4): Learn to Debug a Bare-Metal PolarFire SoC Application with Renode

In Session 3, we will show you the pse-blinky demo example that emulates a PolarFire™ SoC system in the Renode development platform with five available harts. You’ll learn how to configure the debug session and how to connect to the hart. We will demonstrate the configuration of the UART analyzer and individual peripherals, then run the example project and simultaneously debug on multiple harts in separate debug sessions. View the Recording.

Agenda
Running “hello world” on each core Using UARTS
Using timers
Demo of execution from eNVM Run and show a debug session

Webinar 4 (Aug. 1): Tips and Tricks for Even Easier PolarFire SoC Debug with Renode

In Session 4, we will recap what has been covered in previous sessions and answer questions that have been raised after each session. We will then demonstrate common Renode™ commands and command syntax and provide an explanation and example of available logging levels. You’ll also learn how to configure SoftConsole launch groups and how to create and use macros for Renode. We will also discuss the primary differences between Renode and Silicon. View the Recording.

Agenda
Common Renode commands
Showcase logging levels
Making launchers
Making macros Renode vs. Silicon

Webinar 5 (Sept. 5): Add and Debug PolarFire SoC Peripherals with Renode

In Session 5 you will learn how to add local memory to a Renode system and execute code. From there, we’ll cover the creation and addition of a timer to the system to create interrupts. A GPIO will then be added, followed by the set up and configuration of MonoDevelop, which is used to create peripherals for Renode. We’ll then create a custom UART that will be added to the system to be compiled just in time. View the Recording.

Agenda
Creating local memory in fabric
Adding a timer on fabric and generate and handle an interrupt
Adding GPIO to fabric

Webinar 6 (Oct. 3): Add and Debug a Pre-existing Peripheral in PolarFire SoC

In Session 6, you will learn to edit the PolarFire SoC fabric configuration to add a UART and build and debug the Renode Emulation Platform in the Mono Develop IDE using Linux. View the Recording

Agenda
Add a UART to the fabric
Building Renode from source
Debugging a model
Supporting Video

Webinar 7 (Nov. 7): Create Custom Models - Filters, Offloading, Acceleration

In this webinar you will learn how to create a custom peripheral from start to finish, compile and build it in the Renode platform.View the Recording

Agenda
Creating a peripheral model
Adding the model to the Renode platform
Building the peripheral with the Renode platform

Webinar 8 (Dec. 5): What's New in SoftConsole v6.2

This webinar will cover the new features released in SoftConsole v6.2 and the changes to Renode configuration and set up. View the Recording

Agenda
Getting Started with Libero SoC v12.3
Using Renode for PolarFire SoC Designs

Webinar 9 (Jan. 9): Getting Started with the Libero® SoC Design Suite v12.3 and Renode

In this webinar we show you the latest Libero tools release with support for the PolarFire® SoC FPGA family using an Early Access Program (EAP) license. We will use the Libero tools to create a simple PolarFire SoC FPGA design using the RISC-V microprocessor subsystem, implement the processor set up in Renode, and then test using SoftConsole. View the Recording

Webinar 10 (Feb. 13): Build Applications for Linux on PolarFire SoC

This webinar will show how to create a Linux application for PolarFire SoC and test them on the Renode emulation platform.

Agenda
Creating a Linux application
Building the application
Testing the application on Renode

Webinar 11 (Mar. 12): Introduction to PolarFire SoC MSS Configuration and Software Flow

This webinar will showcase the PolarFire SoC Microprocessor Subsystem Configuration Tool (MSS Configurator) with examples.

Agenda
Introduction to the MSS Configurator
System setup with the MSS Configurator

Webinar 12 (Apr. 9): Two baremetal Applications on PolarFire SoC

In this webinar you will learn how to configure the PolarFire SoC system to run two distinct applications on separate harts using memory protection (PMP), expanded memory (LIM), and coherent message sharing.

Agenda
Configuring the PolarFire SoC system
Configuring the software
Running software on the system
Debugging the system

Webinar 13 (May 14): Linux + Real-Time (AMP Mode) on PolarFire SoC

This webinar will show how to configure a PolarFire SoC system for asymmetric multiprocessing and how to run Linux on 4 harts with a baremetal application running in real-time on the 5th hart

Agenda
Configuring the system in AMP mode
Building Linux
Building the realtime application
Debugging

Mi-V Partners

		Adacore is the leading provider of commercial software solutions for Ada, C and C++, helping developers build safe, secure and reliable software that matters.
		Amazon FreeRTOS is open source and extends the FreeRTOS kernel with libraries making it easy to connect to cloud services and edge devices. Amazon FreeRTOS support is now available for RISC-V based MCUs.
		Antmicro’s Renode Simulation platform offers multiple connected virtual device setups within the same environment enabling ease of development for customers without the hassle of C programming.
		ARIES Embedded offers hardware products (modular systems and custom designs), services for IP-development and software development (FreeRTOS, U-Boot, Linux) based on Microsemi's Polarfire FPGA and SoCs.
		Digital Core Technologies offers design services covering the entire Life Cycle of a product. This includes Hardware Designs (High Speed, High-Density Digital, Analog, Power and RF), Embedded Logic Ware and Embedded Software
		DornerWorks specializes in FPGA Design and Engineering, Embedded Software and Hardware Development. Their expertise includes designs for the Aerospace, Medical, Automotive and IoT markets.
		Emcraft is a leading provider of System-on-Module (SoM) solutions. They provide production-ready, self-maintained Linux BSPs and Software distributions for all of their SoM Solutions.
		Emdalo Technologies a software engineering development company specializing in delivering solutions in Embedded Systems, Machine Learning, AI, Information Security and IIoT Applications.
		Enclustra offers highly-integrated FPGA modules (SoM) and FPGA-optimized IP cores. and provides services covering the whole range of FPGA-based system development from high-speed hardware or HDL firmware through to embedded software.
		Express Logic provides comprehensive X-WARE IoT Platform for embedded developers targeting FPGAs. The THREADX RTOS has been ported to the RISC-V Soft CPU on the PolarFire MPF300-EVAL-KIT evaluation board.
		Hex Five Security, Inc. is the creator of MultiZone™ Security, the first trusted execution environment for RISC-V, which provides policy-based hardware-enforced separation for an unlimited number of security domains, with full control over data, code, peripherals and interrupts.
		IAR Embedded Workbench is an integrated development environment for building and debugging embedded applications using C and C++. The toolchain offers leading code quality, size and speed; extensive debug with simulator and hardware debugging support.
		Imperas supports Microsemi's RISC-V based SoC FPGAs with the Mi-V FreeRTOS Extendable Platform Kit (EPK), tools to help in development, porting, debug and test.
		Mentor enables embedded development for a variety of applications including automotive, industrial, smart energy, medical devices, and consumer electronics with their Linux products and Nucleus RTOS.
		Micrium provides high-quality embedded software components in the form of engineer-friendly source code coupled with unsurpassed documentation and customer support.
		Phytec is a leading provider of SoM solutions based on application processors and FPGAs. Phytec also offers services: systems integration, hardware and software design, mechanical design and manufacturing.
		SecureRF provides security solutions for embedded systems and wireless sensor technologies. SecureRF is a CompanionCore partner of Microsemi and offers optimized IP cores for Microsemi FPGAs.
		SiFive builds customized silicon based on the open-source RISC-V ISA. SiFive offers customizable RISC-V CPU Core IP for use in Microsemi FPGAs reducing time-to-market and cost.
		Sundance DSP is a world-wide supplier of high-performance DSP and FPGA processor boards (SoM) and I/O modules for high performance, parallel processing applications such as imaging, radar, sonar, industrial control and military.
		Technolution provides tailor-made solutions such as Fault Tolerant RISC-V soft cores, High speed Interfaces, BSP and Drivers, Real-time Video transport, and High-end Board design.
		Trenz Electronic develops, manufactures, integrates and sells FPGA and SoC modules (SoM) with main focus on application specific HDL and FPGA design, hardware and software development.
		UltraSoC is deeply involved in defining the debug architecture for RISC-V standards. UltraSoC is the first company to offer a RISC-V processor trace solution, supporting both open source and commercial processors.
		WindRiver VxWorks is the world's leading real-time operating system. WindRiver extends VxWorks support to PolarFire SoC.
		wolfSSL provides Open Source, lightweight and embedded security solutions with an emphasis on speed, size, portability, features, and standards compliance. Their products include wolfSSL, wolfCrypt, yaSSL and wolfSSH.
		The Zephyr Project is an open source collaborative effort to build a small, scalable RTOS. Zephyr OS has been ported on the Mi-V RISC-V Soft CPU deployed on the IGLOO2 FPGA on the Evaluation Kit M2GL-EVAL-KIT.

Articles and News

05/22/2019 - IAR Systems: IAR Systems Takes RISC-V to the Next Level with Launch of Professional Development Tools

05/03/2019 - EE Times: Spacecraft Communications Call for Sophisticated Data-Transmission Techniques

04/29/2019 - Electronics 360: 4 Reasons to use RISC-V for aerospace and defense applications

04/20/2019 - Design News: 8 RISC-V Companies to Watch

03/26/2019 - All About Circuits: Running Hard Real-Time Applications and Linux on PolarFire SoC

02/26/2019 - UltraSoC: UltraSoC demonstrates advanced multicore debug at Embedded World 2019

02/14/2019 - EBN: Open Source Hardware Benefits Procurement Practices

02/01/2019 - Aerospace & Defense: Using RISC-V to Simplify Data Logging in Space

12/04/2018 - LinuxGizmos.com: World’s first RISC-V-based FPGA SoC runs Linux

12/04/2018 - New Electronics: Microchip unveils new class of SoC FPGA

12/04/2018 - ElectronicsWeekly: Microsemi adds to RISC-V based FPGAs

12/04/2018 - EE Times: RISC-V Takes a Leap Forward

12/04/2018 - Microchip: Industry's First RISC-V SoC FPGA Architecture Brings Real-Time to Linux, Giving Developers the Freedom to Innovate in Low-Power, Secure and Reliable Designs

09/10/2018 - RISC-V Foundation: RISC-V Fall Newsletter 2018

06/05/2018 - RISC-V Foundation: RISC-V Summer Newsletter 2018

05/07/2018 - Microchip: Microsemi and SiFive Launch HiFive Unleashed Expansion Board, Enabling Linux Software and Firmware Developers to Build RISC-V PCs for the First Time

04/17/2018 - Microchip: Microsemi's Mi-V Ecosystem Continues to Expand as New Member Antmicro Joins to Develop Mi-V RISC-V Processor Subsystems for PolarFire FPGAs

04/05/2018 - SatMagazine: Improving Space Systems Designs Using FPGAs with RISC-V Cores

03/26/2018 - Embedded Systems Engineering: Plugging Security Vulnerabilities in Servers and Data Center Architectures

02/26/2018 - Semiconductor Engineering: RISC-V Gains Its Footing

02/23/2018 - RISC-V Foundation: RISC-V Winter Newsletter 2018

02/15/2018 - ExpressLogic: Express Logic’s X-Ware IoT Platform® Brings Industrial-Grade IoT Support to RISC-V Architecture

02/13/2018 - ExpressLogic: Express Logic, Inc. announces that its industrial-grade X-Ware IoT Platform®—powered by the industry-leading ThreadX® RTOS—provides turnkey support for Microsemi’s Mi-V RISC-V instruction set architectures (ISAs)

02/13/2018 - Military Embedded Systems: Using RISC-V in FPGAs for strategic defense systems

01/31/2018 - Electronic Design: 11 Myths About the RISC-V ISA

10/20/2017 - RISC-V Foundation: RISC-V E-Newsletter October 2017

10/19/2017 - Microsemi: Microsemi Launches Mi-V Ecosystem to Accelerate Adoption of RISC-V

06/18/2017 - Embedded Computing Design: Growing the pie: Eclipse-based Windows IDE gives more access to RISC-V developers

06/16/2017 - Elektronik Praxis: SoftConsole 5.1: Windows Eclipse IDE with support for RISC-V command sets

06/16/2017 - New Electronics: Microsemi launches Windows-based RISC-V IDE

06/15/2017 - Microsemi: Microsemi Announces SoftConsole v5.1, the World's First Freely Available Windows-Hosted Eclipse Integrated Development Environment Supporting RISC-V Open Instruction Set Architecture

06/15/2017 - Tech Design Forum: Microsemi builds Windows IDE for RISC-V

06/15/2017 - Markt & Technik: Free Windows IDE for RISC-V

06/15/2017 - Radio-electronics.com: Microsemi Announces SoftConsole v5.1, for Windows

06/15/2017 - Electronic Specifier: IDE showcased at Design Automation Conference in Texas

11/16/2016 - Microsemi: Microsemi is First FPGA Provider to Offer Open Architecture RISC-V IP Core and Comprehensive Software Solution for Embedded Systems

07/16/2016 - Microsemi: Microsemi Sponsors Design Training For Embedding RISC-V in its SmartFusion2 SoC FPGAs during Hands-on Tutorial Session

07/14/2016 - Microsemi: Microsemi's Ted Speers Joins Inaugural RISC-V Foundation Board of Directors to Support Company's IoT Growth Using New Emerging ISA Standard

Renode
Reference Material	Description
SoftConsole Release Notes	SoftConsole and Renode installation instructions and release notes
Renode Documentation Renode Website	Complete documentation on Renode
Mi-V_RV32IMA_L1_AHB Handbook Mi-V_RV32IMA_L1_AXI Handbook Mi-V_RV32IMAF_L1_AHB Handbook	Handbooks for Mi-V soft CPUs
RISC-V ISA Specification RISC-V ISA Privileged Specification RISC-V Debug Specification	RISC-V Specification Documentation
Target: SoftConsole	SoftConsole Software and documentation

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