ZL30112
SLIC/CODEC PLL
Overview
| The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices.
The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable. |
Simplified Block Diagram
Typical Applications
- Synchronizer for POTS SLIC/CODEC
- Rate convert NTR 8 kHz or GPON physical interface clock to TDM clock
Features & Benefits
- Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input
- Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse
- Automatic entry and exit from freerun mode on reference fail
- Provides DPLL lock and reference fail indication
- DPLL bandwidth of 29 Hz for all rates of input references
- Less than 0.6 nsecpp intrinsic jitter on all output clocks
- 20 MHz external master clock source: clock oscillator or crystal
- Simple hardware control interface
Resources
Documentation
Application Notes
- ZLAN-68 - List of Oscillators & Crystals that can be used with Zarlink's PLL, Digital Switches with Embedded PLL & Timing over Packet Devices
- ZLAN-178 - Synchronizer Power Supply Decoupling and Layout Practices
Applications
Typical Applications
- Synchronizer for POTS SLIC/CODEC
- Rate convert NTR 8 kHz or GPON physical interface clock to TDM clock
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Ordering
Clock Generator - 0.008MHz to 19.44MHz In - 8.192MHz Out - 32-Pin QFN EP - Tray
| Distributor | SKU | Stock | MOQ | Pkg | |
|---|---|---|---|---|---|
| Microchip Technology Inc. | .. | .. | .. | .. | Buy Now |
| Arrow Electronics | ZL30112LDG1 | 34 | 1 | .. | Buy Now |
| DigiKey | ZL30112LDG1-ND | 490 | Tray | No Stock | |
| Mouser | 494-ZL30112LDG1 | 247 | 1 | Tray | Buy Now |
