MIV_RV32IMA_L1_AXI |
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Overview
The MIV_RV32IMA_L1_AXI is a softcore processor designed to implement the RISC-V instruction set for use in Microsemi FPGAs. The processor is based on the Rocket-Chip RISC-V core. The core includes an industry-standard JTAG interface to facilitate debug access, along with separate AXI bus interfaces for memory access and support for 31 dedicated interrupt ports. Key Features:
Supported Devices:
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Alphanumeric Parameter | Value |
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Functional Category | Processors & Peripherals |
Device Family | PolaFireSoC,PolarFire,RTG4,IGLOO2,SmartFusion2 |
License | |
Core Provider | Microchip |
Application | Aerospace,Automotive,Industrial,Medical |
This part can be found in the following product categories: