ZL30163
Dual Channel Network Synchronization Clock Translator
Overview
The ZL30163 is a dual channel Network Synchronization Clock Translator combining two programmable DPLLs / NCOs with four programmable synthesizers.The device is a fully compliant SEC (G.813) and EEC (6.8262) flexible rate conversion DPLL. It is capable of accepting or generating any frequency from 1Hz to 750MHz on up to eleven input references and up to sixteen output clocks.
Key Features
- Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion Digital Phase Locked Loop (DPLL)
- Two independent, programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronizae to any clock rate from 1Hz to 750MHz
- Four programmable synthesizers generate any clock rate from 1Hz to 750MHz with maximum jitter below 0.62 ps rms
- Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
- Digital PLLs filter jitter from 0.1mHz up to 1kHz
- Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair
- Automatic hitless reference switching and digital holdover on reference fail
- Reference inputs:
- Nine reference inputs configurable as single ended or differential
- Two additional single ended reference inputs
- Any Output Frequency:
- Eight LVPECL output clocks
- Eight LVCMOS output clocks
- Up to four unique customer defined default configurations, including input/output frequencies, are available via OTP (One Time Programmable) memory
- Easy Configuration and dynamic programming via SPI/I2C interface
- Operates from a single crystal resonator or clock oscillator
Resources
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