ZL30167

Overview

The ZL30167 is a dual channel Clock Translator combining two programmable DPLLs / NCOs with four programmable synthesizers to support any communication service over optical networks. For applications that require synchronizing to a 1PPS input, the ZL30167 supports a sync pulse/clock pair feature.  Any of the inputs can be used for a 1PPS signal shared with any other input for a reference frequency.  The output will be synchronized to the input reference and will be phase aligned to the 1PPS input.  This unique feature allows a line card with a crystal to be used for synchronizing to a 1PPS input.  This normally requires a PLL with a 30mHz bandwidth and TCXO.  With very low power consumption, the ZL30167 operates from a single crystal resonator or clock oscillator. It is capable of accepting any frequency from 1kHz to 750MHz on up to eleven input references and generating any frequency from 1Hz to 750MHz on up to sixteen output clocks.

Applications/Uses

• OTN muxponders and transponders
• 10 Gigabit Line cards
• Synchronous Ethernet, 10 GBASE-R and 10 GBASE-W
• SONET/SDH, Fibre channel, XAUI
• Timing translation for optical, storage, networking and broadcast video applications

Key Features

• Two Independent clock channels
• Two programmable digital PLLs/Numerically Controlled Oscillators (NCOs)
• Programmable digital PLLs synchronize to any clock rate from 1 kHz to 750 MHz
• Four Programmable synthesizers generate any clock rate from 1 Hz to 750 MHz
• Any input reference can be fed with sync (frame pulse) or clock
• Programmable DPLLs can synchronize to sync pulse and sync pulse/clock pair
• Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC
• Digital PLLs filter jitter at 5.2 Hz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
• Automatic hitless reference switching and digital holdover on reference fail
• Reference inputs:
  • Nine reference inputs configurable as single ended or differential
  • Two additional single ended LVCMOS reference inputs
  • LVCMOS (1kHz to 177.5 MHz)
  • LVDS or LVPECL (1kHz to 750MHz)
• Any Output Frequency:
• Eight LVPECL output clocks
• Eight LVCMOS output clocks
• Easy Configuration: field programmable via SPI/I²C interface
• Modes of Operation:
  • Integer, Fractions or Ratio (FEC support)
  • Each clock channel can work as either PLL or NCO
• Reduces BOM Cost and Board Space:
  • Replaces multiple devices
  • Package: 13 x 13mm
• Low Power: < 2W
• Increases Design efficiency:
  • Easy programming: SPI/I²C
  • Up to four unique customer defined default configurations, including input/output frequencies, are available via OTP (One Time Programmable) memory