Synopsys
Overview
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at www.synopsys.com.
Products and Services
The Synopsys FPGA design solution comprises high-quality, high-performance, and easy-to-use FPGA implementation, verification, and debug tools. Designers using the Synopsys FPGA design tools gain fast time-to-results for complex FPGAs, area optimization for cost and power reduction, leading HDL language support, and incremental and team design capabilities for faster FPGA design development. The Synopsys FPGA design tools provide additional value by offering DesignWare ® IP integration, links to high-performance functional verification with VCS ®, static verification for clock domain crossing analysis and lint with SpyGlass, integration with Synphony Model Compiler, and an ASIC compatible synthesis flow for FPGA-based prototyping.
Synplify Pro ® Logic Synthesis for FPGA Implementation*
The Synplify Pro FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology ® (BEST™) performs optimization first, at a high level, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. It supports implementation in FPGA devices from Microsemi using a single easy-to-use interface and has the ability to perform incremental synthesis and intuitive HDL code analysis. Learn more about Synplify Pro.
Identify ® RTL Debugger - Simulator-live Visibility into Hardware Operation*
The Identify RTL debugger allows users to instrument their RTL and then, directly in their RTL code, debug the implemented FPGA on live, running hardware. The software verifies a design in hardware, similar to simulation -œ only much faster and with in-system stimuli. The Identify RTL debugger allows users to designate sample triggers, navigate their design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code or they can be viewed in the Identify RTL debugger's, or any third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design. Design iterations can be rapidly accomplished using incremental place and route. Learn more about Identify.
Synphony HLS - High Level Synthesis from Language and Model-based Design*
Synphony is a language and model-based high level synthesis (HLS) technology that provides an efficient path from algorithm concept to silicon. Designers can construct high level algorithm models from C/C++ languages or high level IP model libraries, and then use the Synphony HLS engine to synthesize optimized RTL implementations for ASIC and FPGA, architectural exploration and rapid prototyping. Learn more about Synphony.
* Microsemi Edition is included with Microsemi's Libero IDE and Libero SoC
SpyGlass – Early Design Analysis Tools Enable Efficient Static Verification of FPGA Designs
The SpyGlass platform provides designers with insight about their design, early in the process at RTL using many advanced algorithms and analysis techniques. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex FPGAs with both in house and third-party IP. SpyGlass Lint and CDC delivers a static verification solution to address the issues related to RTL coding best practices, design reusability and multiple asynchronous clock domain crossings (CDC) such as metastability, data re-convergence, FIFO integrity, and more.
For information about pricing and obtaining products or services, please contact Synopsys directly.
Library Information
Synopsys tools use the synop library. For tools that support Microsemi products, please visit the Synopsys SVP Cafe.
For more information on Synopsys' products, visit their website at www.synopsys.com.
Contact Information
For additional information, contact Synopsys at:Synopsys, Inc.
690 East Middlefield Rd.
Mountain View, CA 94043
USA
Tel: +1 650.584.5000
+1 800.541.7737Web: www.synopsys.com
