ZL30416
SONET/SDH Clock Multiplier PLL
NOT RECOMMENDED FOR NEW DESIGNS
Overview
The ZL30416 is an Analog Phase-Locked Loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30416 generates low jitter output clocks suitable for Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 applications.
The ZL30416 accepts a CMOS compatible reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 or 77.76 MHz and generates a differential LVPECL output clock selectable to 19.44, 38.88, 77.76, 155.52 or 622.08 MHz and a single-ended CMOS clock at 19.44 MHz. The ZL30416 provides a lock indication.
Features & Benefits
- Ultra low jitter generation of 4psRMS (40pspk-pk) maximum.
- Surpasses Telcordia GR-253-CORE jitter requirements for OC-3 and OC-12.
- Surpasses ITU-T G.813 jitter requirements for STM-1 and STM-4 rates.
- Easily accommodates the most stringent jitter requirements imposed by SONET/SDH devices.
- Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 MHz or 77.76 MHz
- Provides one differential LVPECL output clock selectable to 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz or 622.08 MHz.
- Provides a single-ended CMOS output clock at 19.44 MHz
- Provides a LOCK indication
- 3.3 V supply
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