Events

Overview

This one-day training event covers advanced topics related to Switchtec PAX Gen3 Advanced Fabric PCIe Switches and PCIe Gen4, and is suitable for systems architects and hardware or software designers.

Location:  2, Sec. 4, Nanjing E. Rd., Songshan District, Taipei City, Taiwan (R.O.C.) , 台北小巨蛋1樓 囍宴軒

Date:  November 14^th, 2017

Transportation:

• Take the Metro
  • Take the MRT "Songshan-Xindian Line (Line 3)" to Taipei Arena Station, Exit 2.
• Take a Bus
  • Take the following bus lines to the Nanjing Dunhua Rd. Station: 33, 248, 262, 262 shuttle, 266 shuttle, 277, 279, 282, 285, 288 shuttle, 292, 292 sub, 306, 306 shuttle, 307, 33, 46, 521, 604, 605 express, 622, 630, 652, 668, 672, 675, 711, 902, 902 shuttle, 903, 905, 905 sub, 906, 906 sub, 909, Boai Bus Route, Dunhua Road, brown 10, brown 9, red 25

Parking:  B1 of Taipei Arena, pay your own share

Cost of Training:  Free

Agenda

• 9:30 – Continental Breakfast and Registration
• 10:00 – Overview of Advanced Topics and MSCC Roadmap
• 12:00 – Lunch Provided On-site
• 1:00 – PAX Advanced Fabric PCIe Gen3 Switch
• 2:00 – Introduction to the NVMe-MI Standard
• (5-10 minute break)
• 3:00 – Gen4 Switchtec Features and PCIe Gen4 Challenges
• 4:30 – Lucky draw

The Switchtec PAX PCIe Gen3 Advanced Fabric switch family comprises programmable and high-reliability PCIe Gen3 switches supporting
high-performance PCIe fabric connectivity, multi-host sharing of single-root input/output virtualization (SR-IOV) endpoints, up to 96 lanes, 48 ports,
24 virtual switch partitions, and hot- and surprise-plug controllers for each port. The switch family also features advanced error containment, comprehensive diagnostics and debug capabilities, a wide breadth of I/O interfaces, and an integrated MIPS processor. PAX switches utilize a system-on-chip architecture that optionally enables customer-differentiated solutions through firmware customization and enhancements.
Applications for the PAX family include scalable multi-host systems, SR-IOV-enabled JBOFs, composable, disaggregated systems, and rack scale architectures.