High Speed Serial Interface/SERDES
Microsemi provides a comprehensive high-speed serial interface solution comprising of configurable functional blocks, IPs and reference designs. The solution is ideal for developing high performance low power applications across verticals from communications and consumer electronics to mission critical applications in commercial aviation.
The high-speed serial interface block, also known as Serializer/De-serializer interface (SERDESIF) integrates several functional blocks to support multiple high speed serial protocols like PCIe, Gbe, XAUI and JESD204B.
- SERDES native rate support from 1G-5Gbps with per lane data rate programming
- Data rates lower than 1Gbps supported with an 3X oversampling reference design (allows 8b/10b transmission down to 333 Mbps)
- Supports 16 lanes at upto 5Gbps each
- Two different reference clocks per SERDESIF block (4 lanes)
- User programmable emphasis and continuous time liner equalization
- Embedded PRBS generation/checking, debug and loopback functions supported with SmartDebug user interface
- For the complete list of all protocols supported along with the speeds, see List of Supported Protocols for SERDES
Low Power, Cost optimised SERDES Solution
- SmartFusion2 and IGLOO2 offer 5G SERDES channels even in smaller devices (<50K LE)
- Max 16 channels of 5G SERDES
- Low SERDES power consumption for data rates upto 5Gbps
An eye diagram of the transceiver running at 5Gbps is shown here:
- CR0021: SmartFusion2 SoC FPGA SERDES Characterization Report
- SERDES Transmission Media Report For SmartFusion2 SoC and IGLOO2 FPGAs
Microsemi offers implementation of PCIe protocol using the high-speed serial interface (SERDESIF) available in the SmartFusion2 or IGLOO2 device families. SmartFusion2 and IGLOO2 have a fully integrated PCIe End Point implementation, in compliance with the PCIe base Specification Revision 2.0 and 1.1.
Microsemi also provides reference designs, application notes and tools to increase productivity and reduce user development time.
The SmartFusion2 and IGLOO2 transceivers provide full support for PCI Express Gen 2.0, including:
- Gen1/Gen2 rates at x1, x2 and x4 links
- Endpoint Topology
- Receiver and Transmit buffers support error correction and coding (ECC)
- Fabric Interface options of AXI3 Master/Slave or AHB32 Master/Slave
- Address translation window support between PCIe and local device address space
SERDESIF PCIe Endpoint blocks available in SmartFusion2 and IGLOO2 are shown below :
|PCIe End Point||0||1||1||Up to 2||Up to 4|
PCIe System Block Diagram
The PCIe system sub-block inside the SERDESIF block implements the PCIe physical layer, data link layer and transaction layer of the PCIe specification. It interfaces with the SERDES block on one side and the FPGA fabric on the other side.
The PCIe protocol stack shown below is fully embedded into each SERDESIF block, 4 SERDES lanes. The entire protocol stack from the physical layer to the user friendly interface of AXI3 or AHB32 is completed in the ASIC portion of the device.
SERDES PCIe Physical layer supports signaling rates of 2.5Gbps and 5.0Gbps with link widths of x1, x2, and x4 and performs link rate and width negotiation. The physical layer also supports the necessary functions of connection detection, electrical idle, and transmit swing adjustments.
Data Link Layer
The data link layer enforces the reliable delivery of packets across the link. PCIe uses credit based flow control and the data link layer performs the initial credit initialization. Once operational, the data link layer provides updates to the current credit conditions as well as handles Ack/Nak generation based on CRC and TLP sequence number as well as data link layer messaging.
The transaction layer is responsible for sending and receiving transaction layer packets (TLP). On the transmit side a retry buffer is provided to hold packets until they are acknowledged by the link partner. Packets will not be entered into the retry buffer unless the link partner has enough credits to handle the packet. The receiver uses a buffer for to hold packets until they are sent to the fabric interface.
The fabric interface can use either a 64-bit AXI3 interface for the master (receive) and slave (transmit) paths to the PCIe interface or a 32-bit AHB interface. The AXI3 interface is useful for high throughput applications with its wider datapath and support for multiple outstanding read requests. The AHB32 interface is useful for less intensive data paths but allows for easy integration with SmartFusion2 Microcontroller SubSystem (MSS). Both interface types support optional address mapping from the PCIe address domain to the local device domain via addressing windows.
The SmartFusion2 and IGLOO2 PCI Express solutions have passed PCI-SIG compliance for Gen2(2.5 Gbps) and Gen2(5.0 Gbps).
- DG0501: SmartFusion2 PCIe MSS HPDMA - Libero SoC v11.6 Demo Guide
- DG0456: SmartFusion2 SoC FPGA PCIe Control Plane Demo - Libero SoC v11.6 Demo Guide
- DG0535: SmartFusion2 PCIe Data Plane Demo using MSS HPDMA and SMC_FIC - Libero SoC v11.6 Demo Guide
- DG0566: SmartFusion2 SoC FPGA PCIe Control Plane Demo For Advanced Development Kit - Libero SoC v11.6 Demo Guide
- DG0517: SmartFusion2 and IGLOO2 PCIe Data Plane Demo using 2 Channel Fabric DMA - Libero SoC v11.6 Demo Guide
Microsemi provides a complete solution for implementing the JEDEC JESD204B serial interface standard. This specification describes a high speed serial for data converters.The CoreJESD204BTX (Transmitter) can be used to interface to DAC devices transmitting digital data to be converted to analog signals and CoreJESD204BRX (Receiver) can be used to interface to ADC devices receiving digital data which can be sampled by the ADC.
Both CoreJESD204BTX and CoreJESD204BRX IP cores support data rates up to 3.2 Gbps at link widths of x1, x2 and x4. The cores can be reconfigured through the APB interface to allow EPCS mode to achieve a higher data rates.
- Enables interfacing of JESD204B compliant ADC/DAC convertors with SmartFusion2 and IGLOO2 devices
- Supports 1, 2 or 4 lanes
- Supports JESD204B subclasses 0, 1 and 2
- Performs word alignment and 8B/10B decoding and encoding
- Recovers link configuration parameters and sources it with user selected parameter values during initial lane synchronization sequence
- Lane alignment sequence generation, buffering, monitoring and correction
- Performs user-enabled frame alignment, monitoring and correction
- Performs octet reconstruction, user-enabled descrambling/scrambling, alignment character generation and error detection
JESD204B IP Cores
Interoperability Test Report
Ethernet, specified by IEEE 802.3 and ranging in data rates from 10/100/1000Mbps up to 100Gbps is the most widely used wired networking standard across the verticals from computing to industrial.
Microsemi provides Ethernet solution comprising of soft IP, reference designs, application notes and tools which enable rapid development of Ethernet interfaces for high performance applications using our SmartFusion2 SoC FPGAs and IGLOO2 FPGAs device families.
The SmartFusion2 Microcontroller Subsystem (MSS) contains an embedded Ethernet MAC and PCS layer, which supports either GMII using FPGA MSIO or SGMII using the SERDESIF. The Ethernet MAC is tightly coupled to the ARM Cortex-M3 of the MSS for Ethernet termination and application layer functions.
IGLOO2 and SmartFusion2 also utilize soft IP blocks to support rates from 10Mbps up to 1000Mbps. Both SmartFusion2 and IGLOO2 provide an embedded XAUI block as part of the SERDESIF.
Microsemi Ethernet Solutions
|10BASE||Embedded MAC or Soft IP MAC||Soft IP MAC|
|1000BASE/SGMII||Embedded MAC or Soft IP PCS/MAC||Soft IP PCS/MAC|
|10GBASE||Embedded XAUI and Soft IP MAC1||Embedded XAUI and soft IP MAC1|
1. The 10G MAC is supplied from a 3rd party IP
The SmartFusion2 embedded MAC can be used with either SGMII or GMII/RGMII physical layer interface. In SmartFusion2 and IGLOO2 a soft IP MAC can be used with an either an SGMII, 1000BASE-X/T, GMII/RGMII or MII/RMM phsical layer interface.
The SmartFusion2 and IGLOO2 support Ethernet using a mix of embedded IP and soft IP which are pre-designed and verified for 10/100/1000Mbps and 10Gbps applications.
- CoreTSE_AHB – 10/100/1000M Ethernet MAC with either a TBI or GMII physical layer. Also includes an embedded DMA controller with AHB interfaces.
- Core10100 – 10/100M Ethernet MAC with MII physical layer
- CoreRGMII – GMII to RGMII interface IP
- CoreRMII – MII to RMII interface IP
- CoreTSE – 10/100/1000M Ethernet MAC with either a TBI or GMII physical layer
- SmartFusion2 Microcontroller Subsystem Ethernet MAC – fully embedded MAC with SGMII or GMII physical layer interface.
- SmartFusion2 and IGLOO2 XAUI – Supported as part of the SERDESIF block.
- DG0634: Running CoreTSE_AHB IP based Webserver on SmartFusion2 using lwIP and FreeRTOS – Libero SoC v11.6 Demo Guide
LiteFast is Microsemi's serial, point-to-point, light-weight protocol for high-speed serial communication. LiteFast enables designers to easily implement high-speed serial links using the SERDES blocks available in Microsemi's SmartFusion2, IGLOO2 and RTG4 devices. The solution comes with pre-synthesized and validated IP cores (Transmitter and Receiver), demo design, and complete documentation which reduces the design and validation time.
Microsemi's LiteFast solution is validated with hardware platform using SmartFusion2 Security Evaluation Kit which has a 90K LE SmartFusion2 SoC FPGA device.
- Supports x 1, x 2 and x 4 lanes per SERDES
- Very little utilization of FPGA logic resources (light weight)
- Idle frame for link establishment and data frame for data transfer
- Idle frame when no data is transmitted
- In-built flow control, word alignment, block alignment, lane alignment and hot-plug support
- Serial full-duplex or simplex operation
- Flow control through token exchange
LiteFast IP Transmitter and Receiver Block Diagram
IP User Guide
Demo Design for SmartFusion2 and IGLOO2
- DG0720: LiteFast IP SmartFusion2 and Igloo2 Demo Guide
- Demo GUI Installer (RAR, 188MB)
Demo Design for RTG4
- DG0729: LiteFast IP RTG4 Demo Guide
- LiteFast RTG4 8bit External Loopback Demo- Design and Programming files (RAR, 93.4 MB)
- LiteFast RTG4 8bit Internal Loopback Demo-Design and Programming files (RAR, 93.5 MB)
- LiteFast RTG4 16bit External Loopback Demo-Design and Programming files (RAR, 97.6 MB)
- LiteFast RTG4 16bit Internal Loopback Demo-Design and Programming Files (RAR, 97.6 MB)
- LiteFast Demo GUI Installer (RAR, 194MB)
- Libero SoC Design Software integrates industry leading synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and push button design flow.
- SmartFusion2 Advanced Development Kit: Microsemi offers 150K LE device inherently integrates reliable flash-based FPGA fabric, a 166 MHz Cortex-M3 processor digital signal processing (DSP) blocks, static random-access memory (SRAM), embedded non-volatile memory (eNVM), and industry-required high-performance communication interfaces— all on a single chip.
- The SmartFusion2 Security Evaluation Kit: Microsemi provides a low-cost platform to evaluate design security and data security features offered by the SmartFusion2 devices. Evaluation board features M2S090TS-FGG484 90K LE device and includes various high speed interfaces such as PCIe Gen2x1, four SMA connectors for SERDES, RJ45 for 10/100/1000 Ethernet. Current measurement test points have been provided to evaluate the low-power capabilities of the device. Using the SmartFusion2 device features and on-board resources,the Security EvaluationKit can be used for quick prototyping of low-power, secure, and highly integrated applications.
- SmartFusion2 Starter Kit: Microsemi provides a cost effective platform for evaluation and development of a SmartFusion2 SoC FPGA based solution. The kit utilizes a miniature mezzanine form factor system-on-module, which integrates the SmartFusion2 device with 64MB LPDDR, 16MB SPI Flash and Ethernet PHY. The baseboard provides easy to use benchtop access to the SmartFusion2 SoC and interfaces
- IGLOO2 Evaluation Kit: Microsemi provides a cost effective platform for evaluation and development of an IGLOO2 FPGA based solution.