RT ProASIC3 FPGAs
The Industry's First Flash-Based, Radiation-Tolerant FPGA for Low-Power Space Applications
RT ProASIC®3 FPGAs are the first to offer designers of space-flight hardware a Radiation-Tolerent (RT), reprogrammable, nonvolatile logic integration vehicle. They are intended for low-power space applications requiring up to 350 MHz operation and up to 3 million system gates.
Unlike all of Microsemi's other radiation-tolerant, space-flight FPGAs, which use antifuse programming technology, devices in the RT ProASIC3 family use flash cells to store configuration information. Positive or negative charge stored on floating-gate transistors is used to hold pass transistors in either the "on" or "off" states, thereby opening or closing connections between routing tracks and logic resources. This use of flash-based interconnects present some unique opportunities and advantages to designers of space-flight electronic hardware:
- The flash cells are reprogrammable. This allows the designer to change the design of the FPGA without removing the FPGA from the board, making prototyping easier. It also allows last-minute design change and code update to provide maximum design flexibility.
- The flash cells are nonvolatile. This means that flash-based FPGAs are standalone devices which do not require the provision of external code-storage devices, unlike SRAM-based FPGAs. This minimizes the board space used, and has an associated saving in mass.
- RT ProASIC3 FPGAs are operating almost at the instant of power-up, which is another advantage of the nonvolatility of the flash programming cells. There is no boot sequence required, as in SRAM-based FPGAs which need to download their configuration code from an external storage device.
- The flash cells do not exhibit single-event upsets in the presence of heavy ion radiation. Therefore no triple-chip redundancy to mitigate configuration upsets is required, unlike SRAM FPGAs.
Microsemi's RT ProASIC3 FPGAs are available in two densities, giving designers the opportunity to integrate large or medium-size designs into these single-chip, live-at-power-up devices.RT ProASIC3 devices use the same silicon design and process as the commercial UMC 0.13 µm ProASIC3EL family. RT3PE600L uses the same silicon as the A3PE600L, and RT3PE3000L uses the same silicon as the A3PE3000L. For more details on the architecture and design used by the RT ProASIC3 devices, refer to the ProASIC3L FPGAs page.
RT ProASIC3 FPGAs are assembled in hermetically-sealed, ceramic packages, which are available as Quad Flat Pack (CQFP), Column Grid Array (CG, with Six Sigma solder columns attached) or Land Grid Array (LG, no solder columns attached). Qualification, inspection, assembly, and testing are performed in accordance with MIL-STD-883 Class B.
RT ProASIC3 FPGAs use the same silicon design and the same 0.13 µm process at UMC as their commercial equivalent ProASIC3EL parts. The ProASIC3 devices have been extensively tested for a variety of radiation effects. The main effects are summarized below. A set of detailed radiation reports is available on the documentation tab and for other families on the Radiation & Reliability Data page.
- Single-Event Latch-Up (SEL)
ProASIC3 devices have been tested in heavy ion environments with various linear energy transfer (LET) rates. No SEL events have been observed up to a projected LET threshold of 68 MeV-cm2/mg.
- Single-Event Upset (SEU)
Heavy ion SEU events have been measured in logic tiles configured as D-type flip-flops, in embedded SRAM memory cells, and in phase-locked loops (PLLs). The embedded FlashROM nonvolatile memory has also been tested but did not exhibit any SEU to LET rates > 96 MeV-cm2/mg. Additionally, proton tests have been conducted on the flip-flops and SRAM memory. SEU results for both heavy ions and protons are tabulated below. The PLLs were observed to lose lock at low LET rates. The onset rate and saturation cross-section appears to be frequency-dependent.
Feature Test Limit Onset LET Saturation Cross-Section Configuration Flash Cells 96 MeV-cm2/mg
No errors observed No errors observed D-Type Flip-Flops 96 MeV-cm2/mg
6 MeV-cm2/mg 2E-7 cm2 per flip-flop SRAM Memory 96 MeV-cm2/mg
1 MeV-cm2/mg 4E-8 cm2 per memory bit FlashROM Memory 96 MeV-cm2/mg
No errors observed No errors observed D-Type Flip-Flops 63.5 MeV Protons 5E-14 cm2 per flip-flop SRAM Memory 63.5 MeV Protons 1E-13 cm2 per memory bit
- Single-Event Transient (SET)
Heavy ion transients have been observed on the global clock networks and on the I/O banks. SET results are tabulated below.
Feature Test Limit Onset LET Saturation Cross-Section Global Clock > 70 MeV-cm2/mg 4 MeV-cm2/mg 2E-6 cm2 per global clock network I/O Bank > 70 MeV-cm2/mg 7 MeV-cm2/mg 2E-6 cm2 per I/O bank
- SEE Mitigation Strategies
Mitigation of the observed single-event effects may be required, depending on the flight-critical nature of the application. If required, mitigation can be accomplished by the instantiation of triple-module redundancy (TMR) of the clock network, the I/O banks and the D-type flip-flops. Synthesis tools have the capability of generating triple-module redundant data paths. TMR is not the most efficient way of achieving mitigation in the combinatorial logic and the embedded SRAM memory. Alternative strategies exist for nonvolatile FPGAs, such as dual-redundant, combinatorial pathways using guard-gates and short delay elements. Such strategies are explained in more detail in the radiation reports.
The single-event effects on the programming circuitry are still being validated. Therefore, programming on orbit is not recommended at this time, until further data is collected.
Total Ionizing Dose
RT ProASIC3 devices have been tested for total ionizing dose (TID) effects in both x-ray and gamma ray environments. Reports are available for both environments. Since the gamma ray data is usually of most interest to radiation effects scientists working on spaceflight systems, the data presented on this page is applicable only to the gamma ray testing.
The TID effect on the device is a degradation of propagation delay through the pass transistors that implement the connections between logic modules and routing tracks. This occurs as charge is deposited in the floating gates, causing them to become either more strongly programmed or less strongly programmed, depending on their original condition. The floating gates which become less strongly programmed are less able to hold the interconnect pass transistors in the "on" state, and this is observable as an increase in propagation delay through the pass transistors. An increase in propagation delay of 10% has been observed at a gamma ray TID level of 25 to 30 kRad with a dose rate of 5 kRad/minute. When testing at a lower dose rate of 1 Rad/minute, which is more representative of the space environment than the 40 krad/minute dose rate used in prior testing, the 10% propagation delay increase was observed at a TID level up to 40 kRad or 15% propagation delay increase at a TID level up to 55 kRad. Additionally, early testing had the programming charge pump VPUMP pin left floating. Better results were achieved in more recent testing, during which VPUMP was connected to ground or 3.3 V, in compliance with datasheet requirements. After more data has been collected and validated, the Designer development software will include this propagation delay derating for designers who wish to account for this increase in propagation delay in their simulation and static timing analysis work.
As with all other RT FPGAs from Microsemi SoC Products Group (formerly Microsemi), each wafer lot of RT ProASIC3 will be sample tested for TID effects in compliance with MIL-STD-883 Class B test method 1019. The results of the TID testing for each wafer lot are available on the documentation tab and for all families on the Radiation & Reliability Data page.
|Embedded RAM/FIFO (without EDAC)|
|Core RAM Blocks||24||112|
|Core RAM kbits (1,024 bits)||108||504|
|User I/Os (maximum)||270||620|
|Speed Grades||Std., -1||Std., -1|
|Screening Level||B, E||B, E|
|CG484 Pin Name List||78 KB||7/2014|
|CQ256 Pin Name List||68 KB||7/2014|
|CG896 Pin Name List||80 KB||7/2014|
|CG484 Daisy Chain Package Drawing||670 KB||10/2015|
|CG896 Daisy Chain Package Drawing||978 KB||10/2015|
|RadHard/RadTolerant Programming Guide||3 MB||8/2001|
|Radiation-Tolerant ProASIC3 Low Power Spaceflight FPGA Fabric Userâ€™s Guide||22 MB||9/2012|
|The Many Flavors of Low-Power, Low-Cost FPGAs White Paper||517 KB||4/2008|
|ProASIC3/E Production FPGAs Features and Advantages White Paper||271 KB||1/2007|
|Flash FPGAs in the Value-Based Market White Paper||65 KB||1/2005|
|RT3PE3000L-CG484-QKN6Y TID Report||2 MB||8/2015|
|RT3PE3000L-CG896-QHR8G TID Report||4 MB||10/2011|
|RT3PE600L-CG484-QJA2H TID Report||4 MB||4/2011|
|RT3PE3000L-CG484-QJA2G TID Report||6 MB||2/2011|
- Contact your local Microsemi Sales Representative
- Search for Available Stock
- Request a Quote
- Request Factory Programming Services
Valid Part Numbers
|RT ProASIC3 Radiation Tolerant FPGAs|
|Part Number||SMD Number||Part Number||SMD Number|