Embedded Processing / MSS
Microsemi offers Embedded Processing solutions for high performance and high reliability applications using low-power SoC FPGAs and FPGAs. The solution includes a comprehensive development environment to build embedded solutions using hard core and soft core processors.
Microsemi SoC FPGA devices contains the industry proven embedded hard core processor ARM Cortex-M3. Microsemi Intellectual Property (IP) cores provide soft core processors to build embedded solutions using the FPGA fabric.
With Microsemi Libero SoC, Software Development tools, IP Cores, Boards and Reference Designs customers can easily develop low power and cost optimized embedded solutions with reduced time-to-market.
Processor Core Offerings
|RISC-V||RISC-V is a new instruction set architecture (ISA) that is now a standard open architecture under the governance of the RISC-V Foundation.||Soft|
|Cortex-M3||High performace 32-bit processor integrating microcontroller features||Hard|
|8051/8051s||8-bit ASM51 compatible controller||Soft|
|ABC||Controller for AMBA APB based designs||Soft|
|MP7||It is compatible with ARM7TDMI-S that has been optimized for maximum speed and minimum size in Microsemi's flash-based FPGAs||Soft|
|Cortex-M1||32-bit ARM Cortex-M1 processor||Soft|
|80188EB||16-bit microprocessor core, executes instruction list compatible with 80188EB microprocessor||Soft|
|80188XL||16-bit microprocessor core, executes instruction list compatible with 80188XL microprocessor||Soft|
|80186||Provides instruction set compatibility to 80186 type design||Soft|
|D68HC11E||Supports complete instructions set of MC68HC11 and compatible with industry standard 68HC11||Soft|
|8-bit microprocessor compatible with 6809 processor||Soft|
|LEON3||32-bit processor compliant with the SPARC v8 architecture||Soft|
Microsemi offers various proprietary and industry standard tools for developing and debugging applications based on hard and soft microcontroller cores. Following table provides the list of embedded tools and features supported by them.
Microsemi provides a standalone executable program called the Firmware Catalog that supports Microsemi SoftConsole, Keil MDK, and IAR Embedded Workbench embedded processor development tool chains targeting the ARM Cortex-M1, ARM Cortex-M3, and Core8051s processors. The Firmware Catalog streamlines locating and generating firmware that is compatible with Intellectual Property (IP) cores used in Microsemi FPGA designs. Firmware can also be delivered through SmartDesign within the Libero environment.
Software drivers are available free of charge and delivered as a C source. These drivers hide the implementation details of peripheral operations behind a driver application program interface (API), so the developer need only be concerned with the peripheral's function.
Soft Processors are microprocessors whose architecture and behaviour are fully described using a synthesizable subset of a hardware description language (HDL). Soft processors can be synthesized for any application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) technology.
Microsemi Intellectual Property (IP) cores offers the broadest selection of soft core processors in the industry.
|Logic Elements||Varies depending on implementation||1179||1848||108||2860||1912|
CompanionCores are available for purchase from our partners and are easily integrated into your design using our Libero tool suite.
|Bus Interface||Internal signals||Internal signals||Internal signals||AHB|
The ARM Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications, specifically developed for high-performance low-cost platforms. The processor is highly configurable enabling a wide range of implementations.
- Hard 166 MHz 32-Bit ARM Cortex-M3 processor
- 1.25 DMIPS/MHz
- 8 Kbyte Instruction Cache
- Embedded trace macrocell (ETM)
- Memory protection unit (MPU)
- Single Cycle Multiplication, Hardware Divide
- JTAG Debug (4 wires), Serial Wire Debug (SWD,2 wires)
- Serial wire viewer (SWV) Interfaces
- 64 KB embedded SRAM (eSRAM) and up to 512 KB embedded nonvolatile memory (eNVM)
- Triple Speed Ethernet (TSE) 10/100/1000 Mbps MAC, USB 2.0, CAN Controller, DDR Bridge (4 Port Data R/W Buffering Bridge to DDR Memory) with 64-Bit AXI Interface
- Two DMA Controllers to Offload Data Transactions from the Cortex-M3 Processor
- 8 Channel Peripheral DMA (PDMA) for Data Transfer (between MSS Peripherals and Memory)
- High-Performance DMA (HPDMA) for Data Transfer (between eSRAM and DDR Memories)
The SmartFusion SoC FPGAs combine the flash-based FPGA fabric with the R1P1 version of the ARM Cortex-M3 hard processor.
- Hard 100 MHz 32-Bit ARM® Cortex-M3 processor
- 1.25 DMIPS/MHz Throughput from Zero Wait State Memory
- Memory protection unit (MPU)
- Single Cycle Multiplication, Hardware Divide
- JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires)
- Single wire viewer (SWV) Interfaces
- Internal Memory
- Embedded non-volatile flash memory (eNVM), 128 Kbytes to 512 Kbytes
- Embedded high-speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, implemented in 2 physical blocks to enable simultaneous access from 2 different masters
- 10/100 Ethernet MAC with RMII Interface 2
- Programmable External Memory Controller, which supports:
- Asynchronous memories
- NOR Flash, SRAM, PSRAM
- Synchronous SRAMs
- 8-Channel DMA Controller to Offload the Cortex-M3 processor
Embedded Solution Development Environment
Microsemi offers a comprehensive development environment for designers to easily implement embedded applications reducing development time and increasing production efficiency.
Microsemi’s flagship software toolset Libero SoC offers a complete firmware design and development environment starting from design entry to programming FPGA silicon.
Microsemi Libero SoC
Microsemi's Libero SoC is the most comprehensive and powerful FPGA design and development software available, providing start-to-finish design flow guidance and support for novice and experienced users alike.
Libero SoC manages the entire design flow from design entry, synthesis and simulation, through place-and-route, timing and power analysis, with enhanced integration of the embedded design flow.
Libero System Builder can be used to configure the SmartFusion2 MSS block (peripherals and memory), FPGA fabric, peripherals and memory. The System Builder wizard creates design based on high-level design specifications. System Builder enables the designer to focus on design specializations instead of on the specific silicon requirements of a SmartFusion2 based design.
SoftConsole provides a flexible, easy-to-use GUI for managing embedded software development projects. Softconsole enables users to quickly develop, edit and debug software programs.
- Available also as a standalone
- GNU C/C++ and SDCC compiler
- Provides a direct interface to microcontroller subsystem (MSS ) of SmartFusion 2 and SmartFusion
- Seamless access to and debug of flash memory
- FlashPro 4/5 compatible debugger sprite
The hardware setup for SoftConsole on the SmartFusion2 Security Evaluation Kit is shown in the Figure below
IAR Embedded Workbench is the integrated development environment (IDE) from IAR Systems for building and debugging embedded applications of SmartFusion2 and SmartFusion. It includes project manager , editor, build and debugger tools.
- C/C++ Compiler
- I-jet and JTAGjet-Trace debugging probes and trace tools
- IAR visualSTATE graphical UML state machine design tool
- 3rd party middle ware tools
The hardware setup for IAR J-Link on the SmartFusion2 Security Evaluation Kit is shown in the figure below
Keil Microcontroller Development Kit (MDK) provides an easy compiling and debugging tools library for embedded applications using MSS block of SmartFusion2 and SmartFusion.
- C/C++ Compiler
- MicroLib run-time library
- ULINK JTAG debugger
The hardware setup for ULINK for running and debugging on the SmartFusion2 Security Evalution Kit is shown in the figure below
Operating Systems RTOS
FreeRTOS™ is a portable, open source, royalty free operating system (OS) intended to serve real-time application requests, typically without buffering delays. It is more reliable and provides one solution for many different architectures and development tools. FreeRTOS is scalable and designed specifically for small embedded systems
SmartFusion2 Advanced Development Kit - Microsemi offers 150K LE device inherently integrates reliable flash-based FPGA fabric, a 166 MHz Cortex™-M3 processor digital signal processing (DSP) blocks, static random-access memory (SRAM), embedded nonvolatile memory (eNVM), and industry-required high-performance communication interfaces— all on a single chip.
SmartFusion2 Security Evaluation Kit - Microsemi provides the low-cost platform to evaluate design and data security features offered by the SmartFusion2 devices. Evaluation board features M2S090TS-FGG484 90K LE device and includes various high speed interfaces like PCIe Gen2x1, four SMA connectors for SERDES, RJ45 for 10/100/1000 Ethernet. Current measurement test points have been provided to evaluate the low-power capabilities of the device. Using SmartFusion2 device features and on-board resources, Security Evaluation kit helps in quick prototyping of low-power, secure and highly integrated applications.
SmartFusion2 Starter Kit - Microsemi provides a cost effective platform for evaluation and development of a SmartFusion2 SoC FPGA based solution. The kit utilizes a miniature mezzanine form factor system-on-module, which integrates the SmartFusion2 device with 64MB LPDDR, 16MB SPI Flash and Ethernet PHY. The baseboard provides easy to use benchtop access to the SmartFusion2 SoC and interfaces.
SmartFusion Development Kit - Microsemi provides a full-featured development platform with extensive memory on-board, multiple networking options, and both digital and analog expansion headers.
- DG0472: Running Webserver and TFTP Server on SmartFusion2 Devices Using lwIP and FreeRTOS - Libero SoC v11.6 Demo Guide
- DG0476: SmartFusion2 - USB OTG Capabilities - Libero SoC v11.6 Demo Guide
- DG0440: Running Modbus TCP Reference Design on SmartFusion2 Devices using IwIP and FreeRTOS - Libero SoC v11.5 Demo Guide
- DG0516: Running the Secure Webserver on SmartFusion2 Devices Using PolarSSL, IwIP, and FreeRTOS - Libero SoC v11.6 Demo Guide
- SmartFusion Modbus TCP Demo Using lwIP and FreeRTOS Users Guide
- AC430: SmartFusion2 I2C Reference Design using Multiple Masters and Multiple Slaves - Libero SoC v11.6 Application Note
- AC388: SmartFusion2 SoC FPGA - Dynamic Configuration of AHB Bus Matrix - Libero SoC v11.6 Application Note
- AC389: SmartFusion2 SoC FPGA - Cache Controller Configuration - Libero SoC v11.6 Application Note
- AC409: Connecting User Logic to AXI Interfaces of High-Performance Communication Blocks in the SmartFusion2 Devices - Libero v11.6
- AC333: Connecting User Logic to the SmartFusion Microcontroller Subsystem App Note
- AC335: Building an APB3 Core for SmartFusion cSoC FPGAs App Note
- AC365: SmartFusion SoC: Running Webserver, TFTP on lwIP TCP/IP Stack App Note
- TU0310: Interfacing User Logic with the Microcontroller Subsystem - Libero SoC v11.6 Design Flow Tutorial
- TU0546: Accessing Serial Flash Memory Using SPI Interface - Libero SoC v11.5 and SoftConsole Flow Tutorial for SmartFusion2 SoC FPGA
- TU0548: Accessing Serial Flash Memory Using SPI Interface - Libero SoC v11.6 SoC and Keil uVision Flow for SmartFusion2 Tutorial
- TU0487: Creating a Libero Project for Firmware Catalog Sample Project - Libero SoC v11.6 and SoftConsole Flow Tutorial for SmartFusion2
- TU0547: Accessing Serial Flash Memory Using SPI Interface - Libero SoC v11.5 and IAR Embedded Workbench Flow Tutorial for SmartFusion2
- TU0559: SmartFusion2 Controller Area Network (CAN) - Libero SoC v11.5 Tutorial