Synphony Model Compiler ME
Microsemi Digital Signal Processing Solution
The Microsemi DSP design flow enables the DSP designer to evaluate an algorithm at a higher level of abstraction using MATLAB and Simulink along with an exhaustive set of DSP blocksets and Microsemi IP. The DSP designer can then follow a seamless and intuitive design flow to translate, optimize, and verify the design at RTL, gate, and physical level with this industry-leading tool set. The result is very short development time and a fast time to market.
Overall DSP Design Flow
The following block diagram shows the DSP design flow. The RTL for DSP design and the top-level system design flow into the Libero SoC that conveniently manages the synthesis, simulation, place-and-route, and programming flow.
DSP Design Flow Example
Starting with a concept, a DSP architect translates ideas into a design in the MATLAB and Simulink environment. DSP blocks supplied by the FPGA or the EDA tool vendors are used at this stage. For instance, targeting the Microsemi FPGA device, the architect or designer uses blocksets supplied by Synphony Model Compiler ME and/or Microsemi IP.
The figure below shows an example of how to create a design in Simulink and use the Filter Design Analysis tool from MATLAB. Start the design capture by dragging in the desired blocks and connecting them up to realize the desired function. Once the design capture is done, the Filter tool provides a convenient facility for analyzing the functional behavior of the filter.
Conversion to Fixed Point
Simulink provides an environment for simulating the design and analyzing its behavior using floating-point and fixed-point accuracies. Simulation can be performed using the built-in stimuli and scope block sets in Simulink. Floating point format provides a baseline performance of the algorithm that helps in the analysis of the fixed-point behavior of the design. As shown in the figure below, the fixed-point tool in Synphony Model Compiler ME helps to automatically change the accuracy of the data. The effects of the tradeoffs can be easily viewed in the scope.
High-Level Synthesis Optimization and RTL Generation
The DSP design can be synthesized into architecturally-optimized RTL by using Synphony Model Compiler ME, which is a high-level synthesis (HLS) tool that performs architectural optimizations from the Simulink specification. These HLS optimizations allow designers to capture the behavior needed for their algorithm without worrying about the specific implementation in hardware. Synphony Model Compiler ME performs transformations and optimizations of the DSP Simulink design based on the Microsemi target device and then generates the RTL.
Synphony Model Compiler ME Optimization Strategies
- Folding: This optimization strategy helps in reducing the area utilization by reusing the same area hardware components (such as multipliers) for multiple streams of data. This results in a very compact design. This optimization is a tradeoff between the area utilization of the hardware and the higher clock rate required to maintain similar data rates.
- Retiming: Retiming optimization is similar to the register balancing optimization done at the RTL Synthesis level; in this case, though, the optimization is done at the system architecture level.
- Multi-Channelization: Once an algorithm has been developed and verified in Simulink, the design can then be replicated over multiple channels. This optimization replicates the design and then automatically applies optimizations which synthesize the time-domain multiplexer logic required for a better area.
More Synphony Model Compiler ME Features:
- Rapid algorithm design and simulation in Simulink
- Easy floating and fixed-point conversion and analysis
- Fully integrated fixed-point blockset of DSP functions
- User-customizable IP blockset
- Automatic generation of code and testbench RTL
- New system-level optimizations for improved performance and area
- VHDL and Verilog language support
- Co-simulation with ModelSim
For further information on Synphony Model Compiler, refer to the Synopsys website.
For use with Microsemi devices, Synphony Model Compiler ME is installed with Libero SoC.
The figure below shows the FPGA implementation environment where the RTL design generated from Synphony Model Compiler ME is synthesized, simulated (optional), and mapped to the FPGA device. There are several tools involved in this process; the design flow has been made easy with the flowchart shown in the tool. You push the relevant buttons in the flow to complete the tasks.
|16 tap CIC Design Samples||4/2012|
|16 tap FIR Filter Design Samples||4/2012|
|16 tap IIR Filter Design Samples||4/2012|
|256 tap FFT Design Samples||4/2012|
|Cordic Exp Design Samples||4/2012|
|Differentiator Design Sample||4/2012|
|Integrator Design Samples||4/2012|
|Qam16withviterbi Design Samples||4/2012|
Synphony Model Compiler ME L2016.03MSP1 (03/2017)
- Synphony Model Compiler ME L2016.03MSP1 Release Notes
- Synphony Model Compiler ME L2016.03MSP1 for Windows
- Synphony Model Compiler ME L2016.03MSP1 for Linux
Synphony Model Compiler ME J-2015.03M (09/2015)
- Synphony Model Compiler ME J-2015.03M Release_Notes
- Synphony Model Compiler ME J-2015.03M for Windows
- Synphony Model Compiler ME J-2015.03M for Linux
How to Obtain Software and License
A software license is required for Synphony Model Compiler ME. The necessary license is included with all Libero Floating licenses. If you are using a Libero Node Locked license, you need to also Request a Free 1 Year License For Synopsys Synphony Model Compiler ME.
Prerequisite Software: In order to run Synphony Model Compiler ME, you must have MATLAB/Simulink by MathWorks installed with a current license.
You can not run Synphony Model Compiler without MATLAB/Simulink.
|The Mathworks Tools||Recommended||Supported||Compatible|
|Versions prior to 2014b
are not compatible.
Synphony Model Compiler ME licenses are available for free.
For more information and to receive your free license, visit Software Licenses and Registration System.
|Synphony Model Compiler ME
License FREE 1 Year
|SmartFusion2, SmartFusion, IGLOO, IGLOO2, ProASIC3, Fusion,
RTAX-S/SL, RTAX-DSP, Axcelerator, ProASICPLUS
|Windows-7 (64 bit), 8.1 (64 bit)
RHEL-6, RHEL-5, SuSE-11 (64 bit)
In order to run Synphony Model Compiler ME, you must have MATLAB/Simulink by MathWorks installed with a current license.
You cannot run Synphony Model Compiler ME without MATLAB/Simulink.
MATLAB/Simulink licenses must be obtained from MathWorks.