Forward Error Correction (FEC) Cores
Enhanced Forward Error Correction Intellectual Property
As service providers upgrade 10G metro and long-haul networks to 100G speed, optical signal-to-noise ratio (OSNR) rapidly degrades due to amplified spontaneous emission noise. Left uncompensated, this OSNR degradation results in unacceptable transmission error rates. Additionally, the complexity of implementation increases exponentially as data rates increase. Enhanced FEC is better able to correct the increased error rates and support error free delivery over longer distances.
Microsemi's patented Continuously Interleaved BCH (CI-BCH™) eFEC IP cores offer the highest performing hard decision eFEC available today. The IP cores are also the industry's only eFEC implementable in FPGA form at 100G. Compared to today's FEC solutions, applying Microsemi's CI-BCH eFEC enables both 40G and 100G backbones to operate over 25% to 50% longer spans, respectively, with lower power, lower cost, and lower latency.
The eFEC cores are offered at 7% and 20% FEC overhead for 40G and 100G implementations, respectively. The 7% overhead version offers 9.35 dB net electrical coding gain (NECG). The 20% version provides up to 10.5 dB NECG.
The CI version of a class of base codes called BCH represents a unique advance in FEC codes, with superior performance to any block codes offered to date. Microsemi's CI-BCH is the industry's first eFEC to solve the implementation complexity issues associated with higher data rates. Both versions of Microsemi's code deliver superior performance at the lowest latency and power dissipation, as well as the smallest gate count, compared to current FEC alternatives.
Ready to migrate your FPGAs or ASICs to 100G? Find your local Microsemi sales office today.
|Product Number||IP Type||Core Detail||NECG||Overhead|
|VSC9800||eFEC Core||40G CI-BCH-3||9.35 dB||6.7 %|
|VSC9802||eFEC Core||100G CI-BCH-3||9.35 dB||6.7 %|
|VSC9803||eFEC Core||100G CI-BCH-3||9.15 dB||6.7 %|
|VSC9804||eFEC Core||100G CI-BCH-4||>10 dB||20 %|