DSP
Overview
Microsemi’s digital signal processing (DSP) solutions include IP cores, reference designs, application notes, tutorials and hardware kits. These resources are designed to easily implement the DSP-based applications using the PolarFire, SmartFusion2 and IGLOO2 devices.
These devices have several built-in features that are suited to meet the following key requirements of a high-performance and low-power DSP application:
- Math-centric and computationally intensive calculations
- High memory bandwidth requirements
- Streaming and data processing
- Ready availability of IP cores for standard algorithms and interfaces
PolarFire FPGA Math Block Features
The fundamental building block in any digital signal processing algorithm is the multiply-accumulate (MACC) operation. PolarFire FPGAs implement a custom 18 x 18 MACC block for an efficient low-power implementation of complex DSP algorithms such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast fourier transform (FFT) for filtering and image processing applications. An optional coefficient ROM can be constructed from logic elements located near the math block.
The key features of the math block functionality are:
- 545 MHz operation
- Up to 1480 18 × 18 two's complement multiplier accumulator with an output width of 48 bits
- Power-saving pre-adder to optimize linear phase FIR filter applications and reduce the math block usage
- Optional pipelining and dedicated buses for cascading
- Dot-product mode for complex multiplies
SmartFusion2 and IGLOO2 Math Block Features
- Up to 240 built-in 18x18 bit hard Math blocks suitable for high performance, power optimized arithmetic DSP operations
- Support fixed point performance up to 102 GMAC/s
- Ideal for low power applications with built-in Flash*Freeze mode and low static power
- Built-in embedded Large SRAMs (18 Kbits) up to 236 blocks suitable for the bulk data storage for DSP applications like Video / Audio processing
- Built-in Micro SRAMs (1 Kbits) up to 240 blocks suitable for low data storage applications like FIR filter coefficients etc
- ARM Cortex-M3 based hard microcontroller sub-system (MSS) in Smart Fusion2 SoC FPGAs ideal to build the DSP based co-processor
Design Flow
Microsemi DSP design flow enables the DSP designer to evaluate an algorithm at a higher level of abstraction using MATLAB and Simulink along with an exhaustive set of DSP blocksets and Microsemi IPs. The DSP designer can then follow a seamless and intuitive design flow to translate, optimize, and verify the design at RTL, gate, and physical level with this industry-leading tool set. The result is short development time and fast time-to-market.
The algorithm implemented in MATLAB Simulink can be converted to synthesizable RTL using Synphony Model Compiler ME. Libero SoC can synthesize, simulate, place and route, and manage programming flow for synthesizable RTL for DSP design and the top-level system design.
DSP Design Methodologies
The following table lists three different design methodologies for implementing DSP applications using Microsemi FPGAs and SoCs.
| DSP Design Methodologies | Description | Software Tools |
| RTL Based Designs |
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| MATLAB Model Based Designs |
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| Processor Based Designs |
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DSP IP
It is easy to get started with Microsemi DSP Cores. All Microsemi IP Cores, either DirectCores or CompanionCores, are accessed by Libero SoC via an automatically managed 'vault'. IP Cores are easily added to your design and configured within Libero SoC.
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List of Direct DSP Cores
- To search for DSP Cores by family set Functional Category to DSP and select preferred family.
- Click on any core link below to see families supported by each core.
| Name | Description |
| CoreCIC | Cascaded Integrator-Comb filters |
| CoreCORDIC | Coordinate Rotation Digital Computer (CORDIC) engine |
| CoreDDS | Direct Digital Synthesizer |
| CoreEDAC | Error Detection and Correction |
| CoreFFT | FFT Processor for Microsemi FPGA |
| CoreFIR | Core generator for finite impulse response filters |
| CoreRSDEC | Reed Solomon Decoder |
| CoreRSENC | Reed Solomon Encoder |
List of Companion DSP Cores
| Name | Description |
| Athena BFFT | Block FFT DSP Core |
| Athena BFFT-M | Block FFT DSP Core |
| Athena PFFT | Pipelined FFT Core |
| Athena PFFT-M | Multi-radix Pipelined FFT |
| Athena PPFFT | Parallel Pipelined FFT |
| Athena PPFFT-M | Multi-radix Parallel Pipelined FFT |
Getting Started
Hardware Tools
- PolarFire Evaluation Kit:- Microsemi offers a 300K LE PolarFire-based kit with DDR4, DDR3 and SPI-flash for a broad class of applications, that is ideally suited for high-speed transceiver evaluation, 10Gb Ethernet, IEEE1588, JESD204B, SyncE, SATA and more.
- SmartFusion2 Advanced Development Kit:- Microsemi offers 150K LE device inherently integrates reliable flash-based FPGA fabric, a 166 MHz Cortex-M3 processor digital signal processing (DSP) blocks, static random-access memory (SRAM), embedded non-volatile memory (eNVM), and industry-required high-performance communication interfaces— all on a single chip.
- The SmartFusion2 Security Evaluation Kit: Microsemi provides a low-cost platform to evaluate design security and data security features offered by the SmartFusion2 devices. Evaluation board features M2S090TS-FGG484 90K LE device and includes various high speed interfaces such as PCIe Gen2x1, four SMA connectors for SERDES, RJ45 for 10/100/1000 Ethernet. Current measurement test points have been provided to evaluate the low-power capabilities of the device. Using the SmartFusion2 device features and on-board resources,the Security EvaluationKit can be used for quick prototyping of low-power, secure, and highly integrated applications.
- SmartFusion2 Starter Kit: Microsemi provides a cost effective platform for evaluation and development of a SmartFusion2 SoC FPGA based solution. The kit utilizes a miniature mezzanine form factor system-on-module, which integrates the SmartFusion2 device with 64MB LPDDR, 16MB SPI Flash and Ethernet PHY. The baseboard provides easy to use benchtop access to the SmartFusion2 SoC and interfaces
- IGLOO2 Evaluation Kit: Microsemi provides a cost effective platform for evaluation and development of an IGLOO2 FPGA based solution.
Demo/Reference Designs
- DG0441: SmartFusion2 SoC FPGA Adaptive FIR Filter - Libero SoC v11.8 SP1 Demo Guide
- DG0438: SmartFusion2 SoC FPGA DSP FIR Filter - Libero SoC v11.7 Demo Guide
- DG0514: IGLOO2 FPGA Adaptive FIR Filter - Libero SoC v11.7 Demo Guide
- DG0504: IGLOO2 FPGA DSP FIR Filter - Libero SoC v11.7 Demo Guide
- DG0630: RTG4 FPGA DSP FIR Filter - Libero SoC v11.8 SP2 Demo Guide
Tutorials
- SmartFusion2 / IGLOO2 Digital Signal Processing Reference Guide
- TU0312: DSP Flow for SmartFusion2 and IGLOO2 Devices - Libero SoC Quickstart and Design Tutorial
Application Notes
Technical Articles
- SmartFusion2 and IGLOO2 PowerAware DSP Design on Lowest Power Mainstream FPGA
- Using FPGAs to Minimize Power in High Speed DSP Intensive System Designs
