RTG4 Radiation-Tolerant FPGAs

High-Speed RT FPGAs for Signal Processing Applications

Overview

RTG4 FPGAs integrate Microsemi’s fourth-generation flash-based FPGA fabric and high-performance interfaces such as serialization/deserialization (SERDES) on a single chip while maintaining the resistance to radiation-induced configuration upsets in the harshest radiation environments, such as space flight (LEO, MEO, GEO, HEO, deep space); high altitude aviation, medical electronics, and nuclear power plant control.

Radiation Performance

RTG4 FPGAs are immune to radiation-induced changes in configuration, due to the robustness of the flash cells used to connect and configure logic resources and routing tracks. No background scrubbing or reconfiguration of the FPGA is needed in order to mitigate changes in configuration due to radiation effects. Data errors, due to radiation, are mitigated by hardwired SEU resistant flip-flops in the logic cells and in the mathblocks. Single Error Correct Double Error Detect (SECDED) protection is optional for the embedded SRAM (LSRAM and uSRAM) and the DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected internal memories.
Here is a summary of RTG4 FPGAs radiation performance:

Configuration memory upsets immunity to LET > 103 MeV.cm²/mg
Single-event latch-up (SEL) immunity to LET > 103 MeV.cm²/mg
SEU-hardened registers eliminate the need for triple-module redundancy (TMR)

Immune to single-event upsets (SEU) to LET > 37 MeV.cm²/mg
SEU rate < 10^–12 errors/bit-day (GEO Solar Min)

SRAM has a built-in error detection and correction (EDAC)

Upset rate < 10^–11 errors/bit-day (GEO Solar Min)
Single error correction and double error detection (SECDED)

Single-event transient (SET) upset rate < 10^–8 errors/bit-day (GEO Solar Min) with optional SET filter
Total ionizing dose (TID) > 100 krad

Reliability and Qualification

RTG4 FPGAs are manufactured on a low power 65nm process with substantial reliability heritage. Flight heritage for RTG4 FPGAs has been achieved on Mission Extension Vehicles (MEV) 1, 2, and CAS-500. The device is also baselined in many US and international programs.

RTG4 FPGAs in CG/LG-1657 and CQ352 packages have been qualified to QML Class V. Refer to this reference guide for the equivalent Defense Logistics Agency (DLA) part number to Microchip’s part number.

Our new RTG4 Sub-QML FPGAs in ball grid array plastic packages FC/FCG-1657 have completed JEDEC qualification, enabling cost reduction and shorter lead times for satellite constellations

Documents

Product Brief

RTG4 FPGAs Technical Brief	689 kB	10/2021
RTG4 ES Description	209 kB	6/2015
RTG4 MS Description	209 kB	8/2015
RT-PROTO FPGA Description	380 kB	9/2017

Datasheet

RTG4 FPGA Datasheet		2.15 MB	9/2021
DS0130: RTG4 FPGA Pin Descriptions Datasheet		292 kB	2/2019

Product Notifications

Please refer to our Product Notifications page for all Customer Notifications, Product Change Notifications, and Product Discontinuation Notifications.

RTG4 PLL Calculator

Please log in here to access the PLL calculator files.
Note: use the same login credentials as those used to download Libero software.

RTG4 PLL Calculator Files Zip Folder

20.93 MB

7/2019

Characterization Reports

CR0028: RTG4 FPGA Characterization Report for XAUI	3 MB	12/2019
CR0031: RTG4 PCIe Characterization Report	433 kB	5/2017
TR0067: RTG4 FPGA SerDes Interoperability with TI TLK2711 Test Report	1.39 MB	5/2021
TR0030: RTG4 FPGA CoreJESD204BRX Interoperability Test Report	1.69 MB	4/2017
MR0014: SmartFusion2 SoC FPGAs, IGLOO2, and RTG4 SerDes Transmission Media Report	1.47 MB	2/2018

Videos / Webinars

Introducing RTG4 FPGAs	5 mins	4/2015
RTG4 Architecture and Features	4 mins	4/2015
RTG4 Reliability and Radiation Effects	5 mins	4/2015
Solving Satellite Signal Processing Congestion Webinar	1 hr	4/2015

White Papers

WP0191: Mitigation of Radiation Effects in RTG4 Radiation-Tolerant FPGAs White Paper	787 kB	4/2015
WP0194: Confidently Deploy Microsemi RTG4 FPGAs in Space-based Systems – A Reliability Overview	365 kB	5/2015
WP0202: Timing Closure on Microsemi SmartFusion2 SoC, IGLOO2, and RTG4 FPGAs	289 kB	1/2016
WP0216: Efficient INT8 Dot Product using Microsemi Math Block	443KB	5/2018

Product Brochures

Radiation-Tolerant FPGAs		2.7 MB	3/2020
Space Solutions Brochure		3.5 MB	10/2019

Packaging

AC190: Ceramic Column Grid Array Application Note	1.97 MB	6/2019
CG1657 Package Outline Drawing	180 kB	8/2016
CB1657 Package Outline Drawing	2.1 MB	4/2015
CG1657 Package Pin Assignment Table	163 kB	7/2016
UG0666: CG1657 Daisy Chain Package User Guide	895 kB	11/2015
CG1657 Daisy Chain Package Pin Connections	17 kB	11/2015
CQ352 Package Outline Drawing	172 kB	1/2017
CQ352 Package Pin Assignment Table	49 kB	6/2018
SpaceWire Pin Mapping from RTG4 ES/MS Silicon to PROTO/Flight Silicon	18 kB	4/2015
Plastic RT4G150-FCG1657M Package Outline Drawing	77 KB	2/2020
FC1657 and FCG1657 Package Pin Assignment Table	15.04 KB	4/2020
FCG1657 Daisy Chain Package	292 KB	6/2020

Note: CG1657 package pin assignment table can be used for CB1657 and LG1657 packages

Radiation & Reliability Data

Total Ionizing Dose (TID) Reports

Please visit our Radiation & Reliability page to view all TID reports.

Single Event Effects (SEE) Reports

Please visit our Radiation & Reliability page to view all SEE reports.

Silicon User Guides

UG0573: RTG4 FPGA DDR Memory Controller User Guide	4.96 MB	04/2021
UG0574: RTG4 FPGA Fabric User Guide	8.03 MB	03/2021
UG0586: RTG4 FPGA Clocking Resources User Guide	3.95 MB	06/2021
UG0567: RTG4 FPGA High-Speed Serial Interfaces User Guide	4.47 MB	06/2021
UG0602: RTG4 FPGA Programming User Guide	0.83 MB	12/2021
UG0576: RTG4 FPGA System Controller User Guide	537.81 kB	03/2021
UG0741: RTG4 FPGA I/O User Guide	1.29 MB	06/2021

Application Notes

Inferring Microsemi RTG4 RAM Blocks App Note	Libero v12.5	2.37 MB	09/2020
AC490: RTG4 FPGA: Building a Mi-V Processor Subsystem Application Note Design Files (ZIP, 354 MB)	Libero v2021.2	1.8 MB	09/2021
AC487: RTG4 FPGA: Temperature Monitor using LM99 Temperature Sensor Design Files (RAR 281MB)	Libero v12.1	7.57 MB	09/2019
AC486: Thermal Management of RTG4 FPGAs in Space Applications	Not Applicable	999 KB	04/2019
AC463: RTG4 Radiation Mitigated Clock and Reset Network Usage Application Note	Not Applicable	301 KB	09/2021
AC474: RTG4 Metastability Characterization Report	Not Applicable	716 KB	06/2018
AC444: Implementing SpaceWire Clock and Data Recovery in RTG4 FPGA Application Note Design Files (ZIP 80.5MB)	Libero v12.6	7.68 MB	01/2021
AC439 & AC453: RTG4 FPGAs Board Design and Layout Guidelines Application Note AC439: RTG4 FPGAs Board Design and Layout Guidelines Application Note Addendum (109.28 KB)	Not Applicable	3.8 MB 100 KB	06/2021 09/2019
AC454: RTG4 SRAM Initialization After Power-up Using µPROM Design Files (ZIP 167 MB)	Libero v12.6	5.79 MB	12/2020
AC459: LX7730 Interface Reference Design Using RTG4 Application Note	Libero v11.7	296 kB	12/2016
AC458: RTG4 CCC Dynamic Configuration Design Files (Zip 169 MB)	Libero v12.6	5.19 MB	12/2020
AC446: Optimization Techniques to Improve DDR Throughput for RTG4 Devices Design Files (Zip 265 MB)	Libero v2021.2	1.88 MB	09/2021
AC465: Migrating a SoftConsole v5.1 Project to SoftConsole v5.2 Application Note	Not Applicable	564 kB	11/2017
AC263: Simultaneous Switching Noise and Signal Integrity	Not Applicable	273 KB	02/2018
AN3216: Reference Clocks for RTG4 SerDes REFCLK Inputs and Interface Circuits	Not Applicable	1.72 MB	09/2019

Software Tools

Migrating RTG4 designs from plastic to ceramic		9/2021
RTG4 FPGA Timing Constraints(Classic Constraint Flow) User Guide	3.2 MB	4/2015
RTG4 FPGA Timing Constraints(Enhanced Constraint Flow) User Guide	2.03 MB	11/2016
RTG4 Macro Library Guide for Libero SoC v12.1		4/2019

Configuration Guides

RTG4 DDR Memory Controller Configuration User Guide		4/2020
RTG4 DDR Memory Controller with Initialization Configuration User Guide		4/2020
RTG4 High Speed Serial Interface (EPCS and XAUI) Configuration User Guide		12/2020
RTG4 High Speed Serial Interface (EPCS and XAUI) with Initialization Configuration User Guide		12/2020
RTG4 High Speed Serial Interface (PCIe, EPCS and XAUI) Configuration User Guide		12/2020
RTG4 High Speed Serial Interface (PCIe, EPCS and XAUI) with Initialization Configuration User Guide		12/2020
RTG4 Clock Conditioning Circuit with PLL Configuration		11/2019
RTG4 FCCC with Enhanced PLL Calibration Configuration User Guide RTG4 FCCC EPLL Calibration Configurator Release Notes -Libero SoCV2021.2		08/2021
RTG4 uPROM Configuration User Guide		4/2020
RTG4 FPGA Two-Port Large SRAM Configuration User Guide		4/2020
RTG4 FPGA Dual-Port Large SRAM Configuration User Guide		4/2020

Demo Guides & Labs

LX7720 + RTG4 Motor Control Demo for Space Applications	Not applicable	229 MB	02/2021
DG0624: RTG4 FPGA SERDES EPCS Protocol Design Design Files (ZIP 255 MB)	Libero v2021.2	6.07 MB	10/2021
DG0622: RTG4 FPGA PCIe Data Plane Demo using Two Channel Fabric DMA Design Files (ZIP 256 MB)	Libero v2021.2	2.38 MB	10/2021
LG0623: RTG4 FPGA Fabric Design Files (Zip 76.9 MB)	Libero v2021.2	2.37 MB	09/2021
DG0625: Interfacing RTG4 FPGA with the External DDR3 Memory Through FDDR Design Files (Zip 131 MB)	Libero v12.6	6.88 MB	12/2020
DG0630: RTG4 FPGA DSP FIR Filter Design Files (ZIP 97.3 MB)	Libero v2021.2	6.3 MB	08/2021
DG0703: Error Detection and Correction on RTG4 LSRAM Memory Design Files (ZIP 80 MB)	Libero v2021.2	4.42 MB	08/2021
DG0729: LiteFast IP RTG4 Demo Guide Design File (ZIP 1.23 GB )	Libero v12.6	3.77 MB	03/2021
DG0713: RTG4 FPGA PCIe Data Plane Demo using Scatter-Gather DMA Controller Design Files (ZIP 261MB)	Libero v2021.2	2.38 MB	10/2021
DG0760: RTG4 SerDes XAUI Design Files (ZIP 721 MB)	Libero v2021.2	2.86 MB	10/2021
TU0565: Low Power RTG4 FPGA Design Files (ZIP 287MB)	Libero v2021.2	5.87 MB	10/2021

Power Analysis

For all Power Estimators please visit our Power Calculators Page.

Errata

ER0193: RTG4 FPGA Errata

328 KB

4/2019

Design Resources

Space System Managers are companion devices that can be used with any Radiation-Tolerant FPGAs

Design Software	The RTG4 family of FPGAs are fully supported by Microsemi Libero® SoC design software, that guides the user through the FPGA design flow and provides seamless design tool integration, as well as project, data file, and log file management. Libero SoC Software is now available for download. The download links can be found in the Libero SoC Software Release Notes.
Software Licensing	RTG4 devices require a Libero Platinum license which can be purchased through sales. Contact your local Microsemi Sales Representative
Design Hardware	The RTG4 Development Kit provides space customers with an evaluation and development platform for applications such as data transmission, serial connectivity, bus interface and high speed designs using the latest Radiation-Tolerant High-Density High-Performance FPGAs family, RTG4. The development board features a RT4G150 device offering more 150,000 logic elements in a Ceramic package with 1,657 pins.
Prototyping Solutions	RTG4 PROTO FPGAs offer a development and prototyping solution than can be used for development and final timing validation of the flight design. As the RTG4 PROTO units use the same reprogrammable Flash technology as the flight units, the PROTO devices can be reprogrammed many times without removing them from the development board. RTG4 PROTO devices use the same silicon and the same packages as RTG4 flight-model FPGAs. RTG4 PROTO device programming is currently enabled in Libero SoC Design Suite. When designing for RTG4 PROTO, customers can use the same device setting in Libero SoC software as for flight models. The RTG4 PROTO prototype units have the same timing attributes as the RTG4 flight units, including support for the same speed grades as the flight parts. The RT-PROTO units are electrically tested in a manner to guarantee their performance over the full military temperature range. Prototype units are offered in non-hermetic, ceramic packages. The prototype units include “PROTO” in their part number, and “PROTO” is marked on devices to indicate that they are not intended for space flight. They are also not intended for applications that require the quality of spaceflight units, such as qualification of spaceflight hardware. RT-PROTO units offer no guarantee of hermeticity, and no Mil-STD-883 class B processing. At a minimum, users should plan on using class B devices for all qualification activities.
Programming & Debug	RTG4 is supported by FlashPro for in circuit programming, FlashPro4 and FlashPro5 both supported Factory Programming Services are also available
IP Cores	Search for RTG4 IP cores Microsemi offers many soft peripherals that can be placed in the FPGA fabric of the device. These include Core1553, CoreJESD204BRX/TX, CoreFIR, CoreFFT, and many other DirectCores.
Partners	Many of Microsemi’s Partners are engaged in development with RTG4 FPGAs
Power Analysis	Leverage our Excel based RTG4 Power Estimator to evaluate power for your design without running through the full design flow. RTG4 FPGA Power Estimator User Guide SmartPower can also provide design specific power analysis for your design implementation within Libero.
IBIS Models	Generic RTG4 IBIS Models are available for signal integrity simulations. Design specific files can also be exported from your design implementation in Libero.
BSDL Models	Design specific files can also be exported from your design implementation in Libero.

Product Selector Guide

RTG4 FPGAs integrate Microsemi’s fourth-generation flash-based FPGA fabric high-performance serialization/deserialization (SERDES) transceivers on a single chip while maintaining resistance to radiation-induced configuration upsets in the harshest radiation environments, such as space flight (LEO, MEO, GEO, HEO, and deep space), high altitude aviation, medical electronics, and nuclear power plant control.