RTSX-SU

Overview

Microsemi's RTSX-SU architecture, derived from the highly successful SX-A sea-of-modules architecture, has been designed to improve upset and total-dose performance in radiation environments with several enhancements, such as SEU-hardened flip-flops, wider clock lines, and stronger clock drivers. Designed in a sea-of-modules architecture, the entire floor of the FPGA is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.

Key Features

• 230 MHz system performance (310 MHz internal)
• Very low power consumption (Up to 68 mW at Standby)
• 3.3 V and 5.0 V mixed voltage
• Configurable I/O support for 3.3 V/5 V PCI, LVTTL, TTL, and CMOS
• 5 V input tolerance and 5 V drive strength
• Secure programming technology prevents reverse engineering and design theft
• 100% circuit resource utilization with 100% pin locking
• Unique in-system diagnostic and verification capability with Silicon Explorer II
• Low-Cost prototyping option deterministic, user-controllable timing
• JTAG boundary scan testing in compliance with IEEE Standard 1149.1 - dedicated JTAG Reset (TRST) Pin
• Highly reliable, nonvolatile antifuse technology
• 32,000 to 72,000 ASIC gates (48,000 to 108,000 system gates)
• Up to 360 user-programmable I/Os
• Hermetically-sealed packages for space applications (CQFP, CCGA/LGA, CCLG)

Radiation Performance

• SEU-Hardened registers eliminate the need to implement TMR
• Immune to Single-Event Upsets (SEU) to LET_TH > 40 MeV-cm²/mg
• SEU Rate < E10-œ10 upset/bit-day in worst-case geosynchronous orbit
• Up to 100 krad (Si) Total Ionizing Dose (TID) - parametric performance supported with lot-specific test data
• Single-Event Latch-Up (SEL) immunity