RTAX-S/SL
Industry-leading Advantages for Designers of Space-flight Systems
Now QML Class V Certified
Overview
RTAX-S radiation-tolerant FPGAs offer industry-leading advantages for designers of space-flight systems. High performance and low-power consumption, true single-chip form factor, and live-at-power-up operation all combine to make RTAX-S the FPGA of choice for space designers. From concept to final integration and flight, Microsemi provides the tools and support to help you successfully integrate your space-flight application into RTAX-S radiation-tolerant FPGAs. Additionally, for space applications that have a need for a lower standby current, Microsemi offers RTAX-SL, the low-power grade option that has half the standby current of the standard product at worst-case conditions.
RTAX-S/SL offers high performance at densities of up to 4 million equivalent system gates and 840 user I/Os for space-based applications. The RTAX-S/SL family, the leading Microsemi product offering for space applications, features SEU-hardened flip-flops implemented without any user intervention, and offers the benefits of user-implemented triple module redundancy (TMR) without the associated overhead.
Key Features
- Highly reliable, nonvolatile antifuse technology
- 30 k to 500 k ASIC gates (250 k to 4 M system gates)
- Up to 540 kbits of embedded memory with optional EDAC protection
- Up to 840 user-programmable I/Os
- Total Dose: 300 kRads (functional) and 200 kRads (parametric)
- SEU less than 1E-10 errors per bit-day (worst-case GEO)
- SEL immune to LETTH in excess of 117 MeV-cm2/mg
- SEU immune to LETTH > 37 MeV-cm2/mg
- Advanced packaging for space applications (CQFP and CCGA/LGA)
- Qualified to QML class Q and QML class V
- Screening: E-Flow (Microsemi Extended Flow), B-Flow (Mil-STD-883B), and V-Flow (MIL-PRF-38535)
- RTAX-SL: Low-power grade option with half the standby current of standard product at worst case conditions
The RTAX-S/SL radiation-tolerant FPGAs comprise a new feature-rich family based on the commercial Axcelerator FPGAs architecture and are specifically designed for space applications. The high density gives designers the advantages of a flexible programmable platform on payload designs, which historically have required radiation-hardened ASICs (RH-ASICs). The increased on-chip functionality gives designers the flexibility to perform last minute design changes without incurring additional costs and without any impact on design time.
RTAX-S/SL offers higher density, higher performance, and more features than previous generations of Microsemi radiation-tolerant FPGAs. SEU-hardened flip-flops use built-in TMR, so they do not require user intervention and do not consume additional programmable logic gates for hardware implementation or host CPU machine cycles for software implementation. SEU-hardened flip-flops are not sensitive to place-and-route locations, thus preserving their SEU immunity.
The RTAX-S/SL family has hot-swap and cold-sparing capabilities, which enable a device to be turned off for minimal power consumption during long space missions and activated only when functionality is required for mission completion.
The RTAX-S/SL FPGAs family possesses an unprecedented 33 million device-hours of reliability data from a flight and commercial equivalent units. There have been no antifuse faults to date. A failure in time (FIT) has been calculated to be less than 10 based on the chi-square distribution, with a minimum upper confidence limit of 60% per JESD74 and an activation energy of Ea = 0.7 eV.
RTAX-S/SL FPGAs are now QML Class V qualified, allowing customers to source the highest quality and reliability FPGAs by simply referencing the DLA Standard Military Drawing (SMD) part numbers. QML Class V parts include 2000 hours life test on each wafer lot and Destructive Physical Analysis (DPA) on each assembly lot. This provides scheduling and cost benefit as customers do not need to perform these tests on their own.
Radiation Performance
- Single-Event Effects
- Testing performed at BNL and Texas A & M 2004
- SEL and SEDR
- Testing performed up to LETTH 117 MeV/cm2-mg (125 ° C)
- No SEL or SEDR observed
- No clock or control logic upset observed
- Single-Event Transient
- High-frequency testing (with NASA Goddard Space Flight Center) up to 150 MHz-no anomalies found
- Logic Single-Event Upset (SEU)
- Cross-section < 1E-9 cm2
- LETTH > 37 MeV-cm2/mg
- SEU per R-Cell < 4E-11 Errors/bit-day (worst case GEO)
- Better than the targeted 1E-10 upsets/bit-day
- Memory SEU
- Cross-section / word ~ 4E-9 cm2, LETTH > 30 MeV-cm2/mg
- EDAC operational, background scrubbing at 2 MHz
- SEU < 1E-10 upsets/bit-day (worst case GEO)
- Cross-section / word ~ 4E-9 cm2, LETTH > 30 MeV-cm2/mg
- Total Ionizing Dose
- Initial results indicate suitability for vast majority of space missions
- No parametric failure up to 200 kRads (Si)
- No functional failure up to 300 kRads (Si)
- Initial results indicate suitability for vast majority of space missions
Total Ionizing Dose (TID)
Total Ionizing Dose (TID) is caused by radiation due to charged particles and gammas in space. This radiation deposits energy by causing ionization in the material. The ionization can change the charge excitation, charge transport, bonding, and decomposition properties of the material, and therefore, the device parameters. The total dose is a cumulative ionizing radiation that an electronic device receives over a specified period of time. The damage is dependent on the amount of radiation and how long it took to accumulate the total dose and is expressed in Radiation Absorbed Dose (RAD). Microsemi publishes Radiation & Reliability Data so that customers can use the radiation data when designing applications with high-reliability needs.Single-Event Effects (SEE)
Ionizing radiation can cause unwanted effects in semiconductor devices. Energetic protons, neutrons, heavy ions, and alpha particles can strike sensitive regions of the transistor, causing various failures, or SEE, such as the following:- Single-Event Upsets (SEUs), which occur when high-energy ionizing particles, such as heavy ions, alpha particles or protons, irradiate a circuit or pass through an integrated circuit, causing a disruption in the system logic.
- Single-Event Latch-Up (SEL) is a condition that causes a device to lose functionality due to a single-event-induced high current state. An SEL may or may not cause permanent device damage, but it does require power strobing of the device to resume normal device operations. Devices with low (< 37.5 MeV-cm2/mg) SEL LETTH are considered unsuitable for space applications.
- Single-Event Transient (SET) upsets are caused by charges accumulated in reverse-biased junctions in CMOS digital circuits at higher frequencies
Product Tables
Product Family
Device | RTAX250S/SL | RTAX1000S/SL | RTAX2000S/SL | RTAX4000S/SL |
---|---|---|---|---|
Capacity | ||||
Equivalent System Gates | 250,000 | 1,000,000 | 2,000,000 | 4,000,000 |
ASIC Gates | 30,000 | 125,000 | 250,000 | 500,000 |
Modules | ||||
Register (R-cells) | 1,408 | 6,048 | 10,752 | 20,160 |
Combinatorial (C-cells) | 2,816 | 12,096 | 21,504 | 40,320 |
Embedded RAM/FIFO (without EDAC) | ||||
Core RAM Blocks | 12 | 36 | 64 | 120 |
Core RAM Bits (k=1,024) | 54 k | 162 k | 288 k | 540 k |
Clocks (segmentable) | ||||
Hardwired | 4 | 4 | 4 | 4 |
Routed | 4 | 4 | 4 | 4 |
I/Os | ||||
I/O Banks | 8 | 8 | 8 | 8 |
User I/Os (maximum) | 198 | 418 | 684 | 840 |
I/O Registers | 744 | 1,548 | 2,052 | 2,520 |
Speed Grades | Std., -1 | Std., -1 | Std., -1 | Std., -1 |
Temperature Grades | E, B, V | E, B, V | E, B, V | E, B, V |
Package | ||||
CCGA/LGA | 624 | 624 | 624, 1152 | 1272 |
CQFP | 208, 352 | 352 | 256, 352 | 352 |
Documents











RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Datasheet |
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17.57 MB | 2/2020 |
CG624 Pin Name List | 125 KB | 7/2014 |
CG1152 Pin Name List | 82 KB | 7/2014 |
CG1272 Pin Name List | 85 KB | 7/2014 |
CQ208 Pin Name List | 42 KB | 7/2014 |
CQ256 Pin Name List | 17 KB | 7/2014 |
CQ352 Pin Name List | 143 KB | 7/2014 |
Product Notifications
Packaging Data
Package Mechanical Drawings |
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11 MB | 5/2015 |
Package Thermal Characteristics and Weights | ![]() |
388 KB | 11/2012 |
Hermetic Package Mechanical Configuration | ![]() |
24 KB | 11/2003 |
Daisy Chain
CG1152 Daisy Chain Package Drawing | ![]() |
1 MB | 8/2005 |
CG1272 Daisy Chain Package Drawing | ![]() |
2 MB | 8/2005 |
CG624 Daisy Chain Package Drawing | ![]() |
1 MB | 9/2007 |
Packaging
AC190: Ceramic Column Grid Array Package App Note | ![]() |
1.97 MB | 6/2019 |
AC193: Ceramic Chip Carrier Land Grid (CC256) Package Handling App Note | ![]() |
207 KB | 11/2003 |
Other
Radiation-Tolerant FPGAs Catalog | ![]() |
2.7 MB | 3/2020 |
Microsemi Space Solutions Brochure | ![]() |
2.8 MB | 10/2019 |
DLA Cross Reference Guide | ![]() |
612 KB | 12/2012 |
RadHard/RadTolerant Programming Guide | ![]() |
3 MB | 8/2001 |
Power Supply Transients on RTAX-S and RTSX-SU Devices White Paper | ![]() |
83 KB | 2/2011 |
RTAX-S Testing and Reliability Update | ![]() |
82 KB | 9/2007 |
Antifuse Programming FAQ | ![]() |
505 KB | 2/2013 |
Understanding Soft and Firm Errors in Semiconductor Devices Questions and Answers | ![]() |
119 KB | 12/2002 |
AX and RTAX-S/SL/D Power Calculator | ![]() |
1 MB | 5/2016 |
Radiation & Reliability Data
Total Ionizing Dose (TID) Reports
Please visit our Radiation & Reliability page to view all TID reports.Single Event Effects (SEE) Reports
Please visit our Radiation & Reliability page to view all SEE reports.Design Resources
STAR-Dundee provides IP cores and products for the Microsemi radiation-tolerant FPGAs including the RTAX and RTG4 devices including SpaceWire and SpaceFibre IP Cores.
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Product Selector Guide
RTAX-S/SL radiation-tolerant FPGAs offer industry-leading advantages for designers of spaceflight systems. High performance, low power consumption, true single-chip form factor, and live-at-power-up operation all combine to make RTAX-S/SL devices the FPGAs of choice for space designers.
Notes:
1. All parts in Column Grid Array packages are now supplied with only Six Sigma solder columns.
2. CGB indicates a column grid array with BAE columns (discontinued in 2007)
3. CGS indicates a column grid array with six sigma columns
4. CG indicates a column grid array with six sigma columns (introduced after the discontinuation of BAE columns, hence no “B” or “S” designator to differentiate between BAE or six sigma columns
5. If ordering the RTAX250S-CG624 device, the package must be specified as 'CG624', not 'CGS624’,
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