Identify ME

Overview

On-chip debugging with Synopsys Identify ME allows the Microsemi FPGA designer to quickly find and correct functional design bugs by probing internal signals of the design directly from the flash FPGA at the system speed. The probed signals are inserted into the RTL and can be viewed directly as part of the RTL view for easy interpretation of the data. An advanced triggering mechanism focuses on a certain area of the design and sets breakpoints in RTL. Identify ME currently supports PolarFire, IGLOO2, IGLOO Series, ProASIC3 Series and mixed signal FPGAs, SmartFusion2, SmartFusion and Fusion devices, through the FlashPro4, FlashPro3 and FlashPro Lite programmers.

Instrument Debug Logic Directly from RTL or Post-Compile Netlists

• Conveniently allows selection of signals and code branches directly from the HDL source code view or Synplify's graphical HDL Analyst views to specify sampling and/or triggering
• Provides full support of all HDL design types (Verilog, VHDL or mixed language)
• Automatically adds the debug logic to the design
• Adds pipelined debug logic so there is minimal or no timing impact on original design.

Complex Trigger Mechanisms and Automation

• Gather only the data you need using unique and complex triggering mechanisms
• Trigger on an event, a series of events, pulse width, or an absence of an event after a period
• Trigger from one clock domain and trigger sampling in another domain
• Supports TCL-based command line interface that allows automation of instrumentation or debug using scripts.

Debugging at Full Speed

• Allows debugging of the design or storing the results from the FPGA running at speed
• Uses the built-in JTAG ports and/or user-selected pins for JTAG interface
• Results are stored on-chip in RAM blocks
• Allows rapid debug of results and the ability to get useful data with less debug logic for heavily utilized FPGAs. Provides immediate feedback on area used for debug logic.
• Allows faster iteration. Design changes are made to the device from Identify ME environment using incremental compile.
• Captures data from any number of signals or depth, depending on available area within the FPGA.
• Expand design signal visibility by selectively viewing up to 8 distinct groups of internal nodes during an Identify Debugger session.
• Remotely access and control FPGA hardware debug sessions over a network connection.

Display and Record Results

• Annotates data directly to the source RTL and you can scroll by clock, back and forward in time
• Displays debug sample data in RTL source as symbolic data or enumerated data type rather than bit-level; ideal for state machines
• Displays debug sample data in Synplify's HDL Analyst views
• The captured data can be displayed in waveform viewers for viewing in a time-based format
• Allows export of VCD-format debug vectors that can be used for simulation
• All nodes are tagged with a sample or trigger icon. Code branch statements (for example, CASE or IF statements) are marked as breakpoints.
  
  

Identify Design Flow 

Before synthesis, the RTL design is instrumented using Identify ME Instrumentor. During instrumentation you to set the sample signals, trigger points for conditional sampling, and trigger breakpoints for allowing specific event-driven sampling of the signals within the design. The Identify ME Debugger then communicates with this debuggable design and captures the operation of the device via the flash device programmer. You can view the sampled signal values directly in the RTL, Synplify's HDL Analyst graphical views, or with any VCD-compatible waveform viewer.