On Chip Debug

Probe insertion is a post-layout process that enables an IGLOO, ProASIC3, SmartFusion, or Fusion designer to insert probes into the design and bring signals out to the FPGA package pins to evaluate and debug the design. While testing a programmed device, the user's design may have inherent logic errors due to inadequate simulation test coverage, external signals that arrived out of sequence, or ignoring of timing setup and hold violations.

 Key Features List

• Post-layout probe insertion is faster than using Synopsys® Identify® ME which requires instrumentation of the design at the RTL level and then running synthesis, layout, and device programming
  • Probe insertion can select internal nets anywhere in the design, connecting the selected signals to unused pins
  • Nets are selected and assigned using the Generate Probed Design feature from the Designer Tools menu
  • If all pins are already assigned a temporary assignment can be used to ‘over-ride’ a less important output
    • Probe insertion has a minimal timing effect on the overall design and is a convenient way to quickly understand logic issues in any design
    • The original saved layout file is retained
    • It can be used if no design modifications are needed
    • Or any necessary modifications can be made to the design so that layout can be run again

Probe insertion enables selection of internal nets anywhere in the design, connection of the selected signals to unused pins, and running of incremental layout to manage the physical connection to the pin. Nets are selected and assigned probes using the Generate Probed Design feature available from the Designer Tools menu. If all package pins are already assigned, a used pin can be temporarily disconnected to enable connection of the probed signal to that pin. The re-routed design can then be programmed into the FPGA, where an external logic analyzer or oscilloscope can be used to view the activity of the probed signal. The package pins and port names are reported in Designer's log file. Once the evaluation is complete, the original saved layout file can be used if no design modifications are needed, or any necessary modifications can be made to the design so that layout can be run again.

Probe insertion has a minimal timing effect on the overall design and is a convenient way to quickly understand logic issues in any design. Post-layout probe insertion is faster than using Synopsys ® Identify ® AE which requires instrumentation of the design at the RTL level and then running synthesis, layout, and device programming.

The Designer Probe Insertion feature is available from the Libero SoC Designer toolbar.

FlashPro On-Chip Debug

FlashPro on-chip debug enables the designer to inspect specific blocks within IGLOO, ProASIC3, SmartFusion, and Fusion family devices via the JTAG interface. On-chip debug features allow the designer to view the programmed contents of embedded FlashROM, nonvolatile memory (NVM), and analog blocks to determine if the data that is actually programmed into these blocks agrees with the pre-programming design parameters. This feature is helpful in the rare event when corruption occurs between the original design file creation and device programming or for final design analysis prior to the FPGA system testing or production.

FlashPro on-chip debug reads the FlashROM data from the programmed FPGA device and automatically compares the data to the programming database (PDB) file generated by Libero SoC. Any mismatch between the device data and the design file is automatically highlighted for the user in the FlashROM inspection interface window.

FlashPro on-chip debug reads the NVM content from the programmed FPGA device and displays the data. The designer can compare the content of the device data to the data from the PDB programming file. This read-only feature displays the programmed NVM data for each user client or for each NVM page address. It can also detect corruption on a per page basis so the designer can quickly locate the problematic areas.

On-chip debug allows the designer to perform a number of inquiries of the programmed SmartFusion and Fusion analog block attributes, including inspection of the analog block data on a channel-by-channel basis. The programmed FPGA device data can be compared to the analog block configurations generated by Libero SoC. Any mismatches are highlighted for the user.

FlashPro on-chip debug also supports viewing of device status information, such as device state, security settings, and power supply voltages supplied to the FPGA.

Launch FlashPro on-chip debug with the Inspect Device button on the FlashPro software tool interface.