SmartDebug
Overview
SmartDebug tools described here are designed for PolarFire, SmartFusion2, IGLOO2, and RTG4 families
NOTE: For IGLOO, ProASIC3, SmartFusion and Fusion please refer to On-Chip Debug Tools.
SmartDebug tool is a new approach to debug the Microsemi FPGA array and SERDES without using an internal logic analyzer(ILA). It is also used to capture FPGA device status and flash memory content. This tool is available in Libero SoC v11.0 software and above that supports probe capabilities in RTG4 FPGAs, SmartFusion2 SoC FPGAs and IGLOO2 FPGAs and also supports device debug features for memory blocks.
SmartDebug utilizes the dedicated and specialized probe points built into the FPGA fabric, which significantly accelerates and simplifies the debug process. It also provides the ability to select different probe points without additional overhead, saving significant recompile time.
The enhanced debug features implemented into the SmartFusion2 and IGLOO2 devices give access to any logic element and enable designers to check the state of inputs and outputs in real time, without any re-layout of the design.
SmartDebug can be accessed from within the Libero design flow, and is also available as standalone software starting from v11.7.
FPGA Hardware Breakpoint Auto Instantiation using SmartDebug (SmartFusion2 and IGLOO2 only):
The FPGA Hardware Breakpoint (FHB) Auto Instantiation feature automatically instantiates an FHB per clock domain using gated clocks. The FHB instances gate the clock domain they are instantiated on. These instances can be used to force halt the design or halt the design through a live probe signal. Once a selected clock domain or all clock domains are halted, you can play or step on the clock domains, either selectively or all at once. The FHB controls in the Smart Debug UI allow you to control the debugging cycle.
FHB comes with two clock domain options - Operate on All Clock Domains and Operate on Selected Clock Domain
The Trigger Signal updates when a live probe is assigned. Clicking on the Arm Trigger, makes the design halts on the next positive edge that occurs on the signal connected to Live Probe.
When a certain number of clock cycles are required before halting the clock domain after triggering, a value between 0 and 255 must be entered for Delay Cycles Before Halt. This sets the FHBs to trigger after the specified delay from the rising edge trigger.
Provision to save the waveform view of the selected active probes using Export Waveform by specifying the number of clock cycles to capture. The waveform is saved to a .vcd file.The FPGA Hardware Breakpoint (FHB) is available in Libero SoC software starting from Libero SoC v11.8
Capabilities:
- SmartDebug has the capability to debug static, pseudo static, and dynamic signals
- It has the ability to probe internal signals without using FPGA fabric, on-chip memory, and I/O resources
- No need to recompile or re-program the FPGA to debug the internal signals
- SmartDebug has observability and controllability features
- Flexibility to change probe points on the fly
- FHB allows users to set breakpoints in logic and step clock cycles like you can do in software development
Methods to debug FPGA Array:
- Live Probe: Two dedicated probes can be configured to observe a Probe Point which is any input or output of a logic element. RTG4 has only one probe point. The probe data can then be sent to an oscilloscope.
- Active Probe: Active Probe allows dynamic asynchronous read and write to a flip-flop or probe point. This will enable a user to quickly observe the output of the logic internally or to quickly experiment on how the logic will be affected by writing to a probe point.
- Memory Debug: Memory debug is used to debug embedded FPGA fabric memories like u/LSRAM and eNVM memory, by reading and writing to it.
- Probe Insertion: Probe insertion is used to insert probes into the design and bring signals out to the FPGA package pins to evaluate and debug the design. This features is only available when SmartDebug is launched from Libero.
- SERDES Debug: SmartDebug is used to debug high speed serial interfaces by utilizing on-chip PRBS features and signal integrity controls.
Training
Design debug is a critical phase of the FPGA design flow. We offer multiple design debug tools and features that allow verification and troubleshooting at the hardware level to complement design simulations.
Designed to support the PolarFire® SoC, PolarFire®, SmartFusion® 2, IGLOO® 2 and RTG4™ FPGA families, our SmartDebug tool is the industry’s best debug tool suite. It enables dynamic real-time signal integrity testing and debugging for FPGA fabric, memories and transceivers, without using an Internal Logic Analyzer (ILA). Additionally, SmartDebug offers the flexibility to change probe points on the fly without recompiling or re-programming the FPGA to debug the internal signals, which accelerates design cycle time.
If you would like to learn how to leverage SmartDebug’s features—including live probe, active probe, probe insertion, FPGA break point, memory debug and transceiver debug GUIs—to reduce your debug cycle time when using our FPGAs, watch the below videos.
Microsemi and Synopsys present: Unique FPGA Debug Capabilities
Short Technical videos (3min-5min)
Debug Design
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Documents
Tutorial and User Guide
SmartDebug for Libero SoC v11.8 User’s Guide
TU0804: PolarFire FPGA: Debugging FPGA Design Using SmartDebug Tutorial
TU0530: SmartFusion2 and IGLOO2 SmartDebug Hardware Design Debug Tools - Libero SoC v11.8 SP1 Tutorial
SmartDebug for Software v11.7 User’s Guide
Device Support
Product Family Support
Families supported in SmartDebug are indicated in the Product Family Support table. The rest of the information on this page relates to these supported families.
Tool Support |
Product Family |
Libero SoC v11.0 and above |
PolarFire, SmartFusion2, |
Standalone SmartDebug v11.7 |
Hardware Debug Support
Tool Support |
Operating System |
Programmer |
Libero SoC |
Windows |
FlashPro-3/4/5 |
Linux |
FlashPro-5 |
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SmartDebug Standalone |
Windows |
FlashPro-3/4/5 |
Linux |
FlashPro-5 |
Software
Software Release Notes and Downloads
SmartDebug is installed as part of Libero SoC by default.
SmartDebug Standalone is also available as part of the Programming & Debug Tools.
What is new in SmartDebug v12.0:
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Fabric Hardware Breakpoint (FHB) solution for PolarFire and RTG4
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PCIe debug support for PolarFire
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Eye monitor enhancement for PolarFire providing continuous transceiver Eye monitoring (Infinite persistent mode)
Supported Platforms
Microsemi tests and supports the latest releases on the specific operating systems shown in the chart below. We are committed to resolving problems encountered by customers on these supported operating systems. We do not support untested operating systems or versions.
Operating System |
Libero SoC |
SmartDebug |
Windows 10 |
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Windows 8.1 |
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Windows 7 |
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RHEL 5 |
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RHEL 6 |
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RHEL 7 |
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CentOS 5 |
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CentOS 6 |
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CentOS 7 |
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Notes:
- Tools are supported on 32 bit and 64-bit operating systems.
- Windows XP is no longer supported
Debug Features
SmartDebug Features |
FPGA Fabric |
Fabric RAM |
eNVM |
SERDES |
IO Usage |
Active Probe |
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Live Probe |
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RTG4=1 SF2/IGL2=2 |
Memory Block |
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Probe Insertion |
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Unused IOs |
Flash Memory |
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SERDES |
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Refer the Overview tab to learn more details on SmartDebug features