Overview

SmartDebug tools described here are designed for PolarFire, SmartFusion2, IGLOO2, and RTG4 families 

NOTE: For  IGLOO, ProASIC3, SmartFusion and Fusion please refer to On-Chip Debug Tools.

SmartDebug tool is a new approach to debug the Microsemi FPGA array and SERDES without using an internal logic analyzer(ILA). It is also used to capture FPGA device status and flash memory content. This tool is available in Libero SoC v11.0 software and above that supports probe capabilities in RTG4 FPGAs, SmartFusion2 SoC FPGAs and IGLOO2 FPGAs and also supports device debug features for memory blocks.

SmartDebug utilizes the dedicated and specialized probe points built into the FPGA fabric, which significantly accelerates and simplifies the debug process. It also provides the ability to select different probe points without additional overhead, saving significant recompile time.

The enhanced debug features implemented into the SmartFusion2 and IGLOO2 devices give access to any logic element and enable designers to check the state of inputs and outputs in real time, without any re-layout of the design.

SmartDebug can be accessed from within the Libero design flow, and is also available as standalone software starting from v11.7.

FPGA Hardware Breakpoint Auto Instantiation using SmartDebug (SmartFusion2 and IGLOO2 only):

The FPGA Hardware Breakpoint (FHB) Auto Instantiation feature automatically instantiates an FHB per clock domain using gated clocks. The FHB instances gate the clock domain they are instantiated on. These instances can be used to force halt the design or halt the design through a live probe signal. Once a selected clock domain or all clock domains are halted, you can play or step on the clock domains, either selectively or all at once. The FHB controls in the Smart Debug UI allow you to control the debugging cycle.

FHB comes with two clock domain options - Operate on All Clock Domains and Operate on Selected Clock Domain

The Trigger Signal updates when a live probe is assigned. Clicking on the Arm Trigger, makes the design halts on the next positive edge that occurs on the signal connected to Live Probe.

When a certain number of clock cycles are required before halting the clock domain after triggering, a value between 0 and 255 must be entered for Delay Cycles Before Halt. This sets the FHBs to trigger after the specified delay from the rising edge trigger.

Provision to save the waveform view of the selected active probes using Export Waveform by specifying the number of clock cycles to capture. The waveform is saved to a .vcd file.

The FPGA Hardware Breakpoint (FHB) is available in Libero SoC software starting from Libero SoC v11.8

Capabilities:

• SmartDebug has the capability to debug static, pseudo static, and dynamic signals
• It has the ability to probe internal signals without using FPGA fabric, on-chip memory, and I/O resources
• No need to recompile or re-program the FPGA to debug the internal signals
• SmartDebug has observability and controllability features
• Flexibility to change probe points on the fly
• FHB allows users to set breakpoints in logic and step clock cycles like you can do in software development

Methods to debug FPGA Array:

• Live Probe: Two dedicated probes can be configured to observe a Probe Point which is any input or output of a logic element. RTG4 has only one probe point. The probe data can then be sent to an oscilloscope.
• Active Probe: Active Probe allows dynamic asynchronous read and write to a flip-flop or probe point. This will enable a user to quickly observe the output of the logic internally or to quickly experiment on how the logic will be affected by writing to a probe point.
• Memory Debug: Memory debug is used to debug embedded FPGA fabric memories like u/LSRAM and eNVM memory, by reading and writing to it.
• Probe Insertion: Probe insertion is used to insert probes into the design and bring signals out to the FPGA package pins to evaluate and debug the design. This features is only available when SmartDebug is launched from Libero.
• SERDES Debug: SmartDebug is used to debug high speed serial interfaces by utilizing on-chip PRBS features and signal integrity controls.