Digital Blocks
Overview
Digital Blocks designs silicon-proven semiconductor Intellectually Property (IP) soft cores for ASIC, SoC, & FPGA developers with system requirements for LCD Display Controller, Display Link Layer, and/or 2D Graphics Rendering Engines.
Digital Blocks offers the DB9000 family of feature-rich, cost-effective display controller IP Cores for leading technology companies requiring TFT LCD panels in their product.
Digital Blocks offers the DB9100 and DB9200 family of programmable 2D Graphics Hardware Accelerator IP Cores, with the DB9100 offering 2D Graphics BitBLT Acceleration and the DB9200 offering 2D Graphics Rendering.
Digital Blocks offers it’s IP Cores in Verilog RTL or Microsemi FPGA and SoC FPGA netlist formats, with easy, streamlined licensing and technical support.
Founded in 1997 and located in Glen Rock, New Jersey, Digital Blocks is located within the Eastern U.S. high-technology corridor.
CompanionCore Partner Products
Digital Blocks is an approved Microsemi CompanionCore Partner offering optimized IP cores for Microsemi FPGAs and SoC FPGAs. For pricing, detail specification, and licensing information , please contact Digital Blocks directly.
DB9000 TFT LCD Display Controller IP Core
Digital Blocks DB9000 TFT LCD Display Controller interface frame buffer memory and an ARM processor via the AMBA AXI/AHB bus fabrics to TFT LCD panels. Display resolutions from 320x240 (QVGA) through 1920x1080 (FHD) are supported.
For High Resolution LCD Panels
- The AMBA AXI 64-bit Master Interconnect connects the Microsemi SoC FPGA DDR Memory Controller to the DB9000 Display Controller for reading of the Frame Buffer.
For Low Resolution LCD Panels
- The AMBA AHB-Lite 32-bit Master Interconnect connects the Microsemi SoC FPGA DDR Memory Controller to the DB9000 Display Controller for reading of the Frame Buffer.
For Both High & Low Resolution LCD Panels – Configuration
- The AMBA AHB-Lite 32-bit Slave Interconnect connects to the DB9000 Display Controller Configuration & Status Registers.
DB9000 TFT LCD Display Controller IP Cores – Latest Datasheets
- DB9000AXI (link to http://digitalblocks.com/files/DB9000AXI-DS.pdf)
- DB9000AHB (link to http://digitalblocks.com/files/DB9000AHB-Lite-DS-V1_2.pdf)
DB9100 - BitBLT 2D Graphics Engine IP Core – Features
- Bit Block Transfer – 3 Independent Memory Sources of data
- On-Screen & Off-Screen Data Block (SRC)
- Off-Screen Fixed Pattern Data Block (PTN)
- On-Screen visible Data Block (DST)
- Raster Operations (ROP) performed on Block Transfers
- 256 Raster Operations
- ROP0, ROP1, ROP2, & ROP3 operations
- Includes industries most popular 15 ROPs
- BitBLT Draw Features
- Pixels, Horizontal & Vertical Lines
- Overlapping & Non-Overlapping Block Transfers
- Solid Color Block Fills
- FONT Monochrome Bitmap to Color Expansion, either Transparent or Opaque
- Rotation Block Transfers: 0, 90, 180, 270 degrees
- Block Stretch on X & Y Axis
- Alpha Blending
- Sprite Moves
DB9200 - 2D Graphics Rendering Graphics Engine IP Core – Features
- Line Draw Graphics Operations
- Pixel Draw
- Line Draw (in any direction)
- Poly Line Draw
- Triangles
- Quadrilaterals
- Circle Draw
DB9100 / DB9200 - Common Features
- Command FIFO or Descriptor Link-List Display Processing Unit
- Simplifies Processor Interface
- Minimizes Processor Overhead
- Frame Buffer & Display Features Supported:
- Display Resolutions up to 8K x 8K
- 4 GB Memory Range
- 8, 16 , 24, & 32 bits-per-pixel color depths
DB9100 / DB9200 – Latest Datasheets
- DB9100AXI (link to http://digitalblocks.com/files/DB9100AXI-DS.pdf)
- DB9100AHB (link to http://digitalblocks.com/files/DB9100AHB-DS.pdf)
- DB9200AXI (link to http://digitalblocks.com/files/DB9200AXI-DS-V-2-0.pdf)
- DB9200AHB (link to http://digitalblocks.com/files/DB9200AHB-DS-V-2-0.pdf)
Standard Deliverables
- Microsemi FPGA targeted netlist or Verilog RTL source code
- Comprehensive testbench suite with expected results
- Synthesis scripts
- Installation & Implementation Guide
- Technical Reference Manual
- Technical Support
Additional Services and Expertise
Digital Blocks provides the following additional services and expertise to help designers optimize IP designs in Microsemi programmable logic devices:
- Customization of CompanionCores
- Annual maintenance for updates and ongoing technical support
- System architecture and design consulting services
Contact Information
For additional information, contact Digital Blocks at:
Digital Blocks, Inc.
PO Box 192
587 Rock Rd
Glen Rock, NJ 07452 USA
Phone: +1-201-251-1281
eFax: +1-702-552-1905
info@digitalblocks.com
