ProASICPLUS

Overview

2nd Generation Reprogrammable Flash FPGAs

ProASIC^PLUS devices with FlashLock® expand on all the features and benefits offered by the ProASIC family. Based on Microsemi flash technology, ProASIC^PLUS devices offer the unique combination of reprogrammability and nonvolatility in a high density programmable logic product. ProASIC^PLUS devices combine the advantages of ASICs with the benefits of FPGAs, enabling engineers to leverage their existing ASIC or FPGA design flows and tools.

Product Features

Key Features

Maximum design security
Reprogrammable
Nonvolatile
Live at power-up
ASIC design flow
Very low power
PLLs and LVPECL I/O
Available in military and automotive temperature grades

Documentation

Datasheets Application Notes Power Calculator FAQ

Datasheets

ProASIC^PLUS Flash Family FPGAs Datasheet (v5.9) (includes Military/Aerospace information) General Description (2.2 MB, Jun 29) Packaging (2.1 MB, Jun 29)	4 MB	1/2010
Automotive-Grade ProASIC^PLUS Flash Family FPGAs	86 KB	5/2021
ProASIC^PLUS Family Flash FPGAs Product Brief	342 KB	1/2010

Packaging Data

Hermetic Package Mechanical Configuration	24 KB	11/2003
Package Mechanical Drawings	11 MB	5/2015
Package Thermal Characteristics and Weights	388 KB	11/2012
Spaceflight FPGAs Catalog	2 MB	5/2012

Application Notes

AC162: RAM Initialization and ROM Emulation in ProASIC^PLUS Devices App Note	615.06 KB	7/2016
AC176: Implementing Multi-Port Memories in ProASIC^PLUS Devices App Note Source Code (ZIP, 10 KB, 07/04)	425 KB	6/2016
AC178: Optimal Usage of Global Network Spines in ProASIC^PLUS Devices App Note	603 KB	7/2003
AC180: Programming ProASIC^PLUS Devices in a Mixed Chain App Note	617 KB	6/2016
AC185: Implementation of Security in Microsemi's ProASIC and ProASIC^PLUS Flash-Based FPGAs App Note Important information about security in Flash FPGAs	915 KB	6/2016
AC192: Floorplanning ProASIC/ProASIC^PLUS Devices for Increased Performance App Note	382 KB	11/2003
AC199: Interfacing ProASIC^PLUS FPGAs with 5V Input Signals App Note	270 KB	3/2004
AC204: Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment App Note	80 KB	5/2004
AC208: Performing Microprocessor Programming For Microsemi's ProASIC^PLUS Devices App Note	595.45 KB	11/2015
AC219: Using ProASIC^PLUS RAM as Multipliers App Note	870.89 KB	11/2015
AC227: How To Use UJTAG App Note Design Files - UJTAG (ZIP, 207 KB)	981.5 KB	4/2015
AC230: Device Serialization for ProASIC^PLUS Devices App Note Design Files (ZIP, 203 KB, 8/05)	107 KB	8/2005
AC232: I/O Features in ProASIC^PLUS Flash FPGAs App Note	754 KB	5/2012
AC247: Macro Constraint Usage in ProASIC^PLUS Design Flow App Note Design Files (ZIP, 270 KB)	1.12 MB	12/2015
AC250: Preloading of ProASIC^PLUS RAM Models in Simulation Using Libero IDE App Note	48 KB	1/2006
AC256: Power-up Behavior of ProASIC^PLUS Devices App Note	539.59 KB	9/2016
AC263: Simultaneous Switching Noise and Signal Integrity Application Note	273 KB	2/2018
AC264: ProASIC^PLUS SSO and Pin Placement Guidelines App Note	451 KB	5/2012
AC276: Board Level Considerations for Microsemi FPGAs App Note		883.7 KB	8/2012
AC281: ProASIC^PLUS RAM/FIFO Blocks App Note	223 KB	8/2006
AC283: Implementing Global Reset for ProASIC^PLUS In-System Programming Applications App Note	83 KB	9/2006
AC300: ProASIC to ProASIC^PLUS Design Migration App Note	110 KB	5/2007
AC306: Using ProASIC PLUS Clock Conditioning Circuits App Note	130 KB	8/2016
AC309: In-System Programming ProASIC^PLUS Devices App Note	1 MB	11/2012
HB: Metastability Characterization Report for Microsemi Flash FPGAs (v1.0)	384 KB	8/2012
HB: Programming Flash Devices (v1.3)	678 KB	12/2011

Power Calculator

ProASIC^PLUS Power Calculator

38 KB

12/2004

FAQ

ProASIC and ProASIC^PLUS Software FAQ

562 KB

1/2003

Product Table

Please refer to the ordering tab for a list of all available part numbers.

Device	APA075	APA150	APA300¹	APA450	APA600¹	APA750	APA1000¹
Maximum System Gates	75,000	150,000	300,000	450,000	600,000	750,000	1,000,000
Tiles (Registers)	3,072	6,144	8,192	12,288	21,504	32,768	56,320
Embedded RAM kbits (1,024 bits)	27	36	72	108	126	144	198
Embedded RAM Blocks (256x9)	12	16	32	48	56	64	88
LVPECL	2	2	2	2	2	2	2
PLL	2	2	2	2	2	2	2
Global Networks	4	4	4	4	4	4	4
Maximum Clocks	24	32	32	48	56	64	88
Maximum User I/Os	158	242	290	344	454	562	712
JTAG ISP	Yes	Yes	Yes	Yes	Yes	Yes	Yes
PCI	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Speed Grades	Std.	Std.	Std.	Std.	Std.	Std.	Std.
Temperature Grades	C, I, A	C, I, A	C,I,A,M,B	C, I, A	C,I,A,M,B	C, I, A	C,I,A,M,B
Package (by pin count)
TQFP	100, 144	100
PQFP	208	208	208	208	208	208	208
PBGA³		456	456	456	456	456	456
FBGA	144	144, 256	144, 256	144, 256, 484	256, 484, 676	896	896, 1152
CQFP²			208		208		208
CCGA/LGA²					624		624

Notes:

Available as Commercial/Industrial and Military/MIL-STD-883B devices.
These packages are available only for Military/MIL-STD-883B devices.
PBGA package is not available for APA150

Design Resources

Design Software

The ProASIC^PLUS family of FPGAs is fully supported by both the Microsemi Libero IDE and the Microsemi Designer FPGA Development software. Microsemi's Designer software provides a comprehensive suite of backend development tools for FPGA development, which includes timing-driven place-and-route, a world-class integrated static timing analyzer and constraints editor, a design netlist schematic viewer, and SmartPower, a tool that allows the user to quickly estimate the power consumption in a design.

Design Hardware

ProASIC^PLUS devices offer in-system programming capabilities. To program a device, the configuration data is supplied through a standard JTAG interface either from a microprocessor, Silicon Sculptor 3 and FlashPro. For applications without a microprocessor, Silicon Sculptor II is best for production volumes while the FlashPro programmers, with their small size and ease of portability, are ideal for prototyping.

For ProASIC^PLUS trace and debugging, Synopsys® provides logic analysis software Identify Microsemi Edition (ME).

IP & Solutions

Search for ProASIC^PLUS IP Cores.

Technology Solutions
	Flash-based FPGAs store the configuration information in on-chip flash cells and require no additional configuration nonvolatile memory in order to load the device configuration data at every system power-up, which reduces cost and increases security and system reliability.
	ProASIC^PLUS is an ideal choice for battery-operated and other power-sensitive applications. With ProASIC^PLUS there is no power-on current surge and no high current transition, which exists on SRAM FPGAs. ProASIC^PLUS also has significantly lower dynamic power consumption than SRAM FPGAs to further maximize power savings. » Low Power
	Greatly simplifies system design, making the device available to perform critical system setup tasks and reduce bill-of-materials costs and PCB area. » Instant-On FPGAs
	The nonvolatile, flash-based ProASIC^PLUS family requires no boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC^PLUS devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security. » Security
	Firm errors do not exist in ProASIC^PLUS FPGAs. The configuration element of ProASIC^PLUS FPGAs, the flash cell, cannot be altered once programmed and is therefore immune to particle effects. » Single Event Effects (SEE)