ProASICPLUS
Overview
Microsemi's 2nd Generation Reprogrammable Flash FPGAs
ProASICPLUS devices with FlashLock® expand on all the features and benefits offered by the ProASIC family. Based on Microsemi flash technology, ProASICPLUS devices offer the unique combination of reprogrammability and nonvolatility in a high density programmable logic product. ProASICPLUS devices combine the advantages of ASICs with the benefits of FPGAs, enabling engineers to leverage their existing ASIC or FPGA design flows and tools.
Key Features
- Maximum design security
- Reprogrammable
- Nonvolatile
- Live at power-up
- ASIC design flow
- Very low power
- PLLs and LVPECL I/O
- Available in military and automotive temperature grades
Documentation
Datasheets Application Notes Power Calculator FAQ
| ProASICPLUS Flash Family FPGAs Datasheet (v5.9) (includes Military/Aerospace information)
|
4 MB | 1/2010 | |
| Automotive-Grade ProASICPLUS Flash Family FPGAs | 86 KB | 2/2004 | |
| ProASICPLUS Family Flash FPGAs Product Brief | 342 KB | 1/2010 | |
| PDN17016: Low-Volume SOC part numbers |  |
0.6 MB | 4/2017 |
| PDN17016: Low-Volume SoC Part Numbers (Addendum) | |
0.5 MB | 5/2017 |
| CN17025: Extending Product Lifecycles with Arrow Supply Assurance | |
0.1 MB | 6/2017 |
Packaging Data
| Hermetic Package Mechanical Configuration | 24 KB | 11/2003 |
| Package Mechanical Drawings |
11 MB | 5/2015 |
| Package Thermal Characteristics and Weights | 388 KB | 11/2012 |
| Spaceflight FPGAs Catalog | 2 MB | 5/2012 |
| ProASICPLUS Power Calculator |  |
38 KB | 12/2004 |
| ProASIC and ProASICPLUS Software FAQ | 562 KB | 1/2003 |
Product Table
Note :
Certain devices will only be available through Arrow Supply Assurance. Effective June 30, 2017, Microsemi will no longer be accepting orders for these products. Orders accepted at Arrow Supply Assurance from June 19, 2017. Please refer to the below CN for more details :
CN17025: Extending Product Lifecycles with Arrow Supply Assurance
Please refer to the ordering tab for a list of all available part numbers.
| Device | APA075 | APA150 | APA3001 | APA450 | APA6001 | APA750 | APA10001 |
|---|---|---|---|---|---|---|---|
| Maximum System Gates | 75,000 | 150,000 | 300,000 | 450,000 | 600,000 | 750,000 | 1,000,000 |
| Tiles (Registers) | 3,072 | 6,144 | 8,192 | 12,288 | 21,504 | 32,768 | 56,320 |
| Embedded RAM kbits (1,024 bits) |
27 | 36 | 72 | 108 | 126 | 144 | 198 |
| Embedded RAM Blocks (256x9) |
12 | 16 | 32 | 48 | 56 | 64 | 88 |
| LVPECL | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| PLL | 2 | 2 | 2 | 2 | 2 | 2 | 2 |
| Global Networks | 4 | 4 | 4 | 4 | 4 | 4 | 4 |
| Maximum Clocks | 24 | 32 | 32 | 48 | 56 | 64 | 88 |
| Maximum User I/Os | 158 | 242 | 290 | 344 | 454 | 562 | 712 |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| PCI | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Speed Grades | Std. | Std. | Std. | Std. | Std. | Std. | Std. |
| Temperature Grades | C, I, A | C, I, A | C,I,A,M,B | C, I, A | C,I,A,M,B | C, I, A | C,I,A,M,B |
| Package (by pin count) | |||||||
| TQFP | 100, 144 | 100 | |||||
| PQFP | 208 | 208 | 208 | 208 | 208 | 208 | 208 |
| PBGA | 456 | 456 | 456 | 456 | 456 | 456 | |
| FBGA | 144 | 144, 256 | 144, 256 | 144, 256, 484 | 256, 484, 676 | 896 | 896, 1152 |
| CQFP2 | 208 | 208 | 208 | ||||
| CCGA/LGA2 | 624 | 624 | |||||
Certain devices have been removed from Product Tables on April 4, 2017. Please refer to PDN17016 for more details :
PDN17016: Low-Volume SOC part numbers
PDN17016: Low-Volume SoC Part Numbers (Addendum)
- Notes:
- Available as Commercial/Industrial and Military/MIL-STD-883B devices.
- These packages are available only for Military/MIL-STD-883B devices.
Design Resources
The ProASICPLUS family of FPGAs is fully supported by both the Microsemi Libero IDE and the Microsemi Designer FPGA Development software. Microsemi's Designer software provides a comprehensive suite of backend development tools for FPGA development, which includes timing-driven place-and-route, a world-class integrated static timing analyzer and constraints editor, a design netlist schematic viewer, and SmartPower, a tool that allows the user to quickly estimate the power consumption in a design.
ProASICPLUS devices offer in-system programming capabilities. To program a device, the configuration data is supplied through a standard JTAG interface either from a microprocessor, Silicon Sculptor 3 and FlashPro. For applications without a microprocessor, Silicon Sculptor II is best for production volumes while the FlashPro programmers, with their small size and ease of portability, are ideal for prototyping.
For ProASICPLUS trace and debugging, Synopsys® provides logic analysis software Identify Microsemi Edition (ME).
Search for ProASICPLUS IP Cores.
| Technology Solutions | |
|---|---|
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Flash-based FPGAs store the configuration information in on-chip flash cells and require no additional configuration nonvolatile memory in order to load the device configuration data at every system power-up, which reduces cost and increases security and system reliability. |
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ProASICPLUS is an ideal choice for battery-operated and other power-sensitive applications. With ProASICPLUS there is no power-on current surge and no high current transition, which exists on SRAM FPGAs. ProASICPLUS also has significantly lower dynamic power consumption than SRAM FPGAs to further maximize power savings. » Low Power |
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Greatly simplifies system design, making the device available to perform critical system setup tasks and reduce bill-of-materials costs and PCB area. » Instant-On FPGAs |
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The nonvolatile, flash-based ProASICPLUS family requires no boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASICPLUS devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security. » Security |
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Firm errors do not exist in ProASICPLUS FPGAs. The configuration element of ProASICPLUS FPGAs, the flash cell, cannot be altered once programmed and is therefore immune to particle effects. » Single Event Effects (SEE) |
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