Fusion
Overview
Fusion® mixed-signal FPGAs integrate configurable analog, large flash memory blocks, comprehensive clock generation and management circuitry, and high-performance, flash-based programmable logic in a monolithic device. The innovative Fusion FPGA architecture can be used with our soft microcontroller (MCU) core as well as the performance-maximized 32-bit ARM Cortex-M1 Processor. Pigeon Point devices (P1-prefixed devices) are used in conjunction with Pigeon Point ATCA IP cores and firmware. Fusion devices are the world's first mixed-signal FPGA platform. In addition to supporting commercial and industrial temperature devices, we offer Fusion FPGAs with specialized screening for extended temperature applications.
The Fusion family includes:
- Fusion
- Extended Temperature Fusion
- M1 Fusion
- P1 Fusion
Key Features
- In-system configurable analog supports a wide variety of applications
- Up to 1 MB of user flash memory
- Extensive clocking resources
- Analog PLLs
- 1% RC oscillator
- Crystal oscillator circuit
- Real-time counter (RTC)
- Available in extended temperature grade from -55 °C to 100 °C
- Immune to configuration loss due to atmospheric neutrons (firm errors)
- Flash Fabric
- Low power
- Secure
- Instant-On FPGAs
- Firm-Error Immune
- Single chip
Fusion Chip Layout
- Integrated Analog to Digital Converter (ADC):Fusion supports an integrated ADC, eliminating the need for external mixed-signal support ICs. With resolutions up to 12 bits and sampling up to 600 ksps, this configurable ADC supports a broad application space. When customers choose to use the calibration option with the Fusion device, they can achieve better than 1 percent accuracy, which makes it ideal for system management applications where this level of accuracy is required.
- Fusion Supports Low Power:The Fusion real-time counter (RTC) includes a programmable 40-bit counter and match register (timer) that generates time-based match events. In addition to use models such as watchdog timer, device lifetime monitoring, and event timer, the RTC can be used to wake the Fusion device out of standby mode, enabling very low-power modes of operation. The No-Glitch MUX (NGMUX) allows the device switch between asynchronous clock domains to occur in a controlled manner. The device switches to a slower clock frequency during periods of relative inactivity, thereby reducing active power consumption.
- Embedded Flash Memory:The Fusion family is the only programmable logic solution to include up to 8 Mbits of embedded flash memory, arranged in 1,024-bit pages. This high-performance, configurable flash memory supports 100 MHz operation and data bus widths of 8, 16, and 32 bits. Utilizing an endurance extender IP block, sections of the flash memory can emulate an EEPROM device to on-chip or off-chip resources. When used in conjunction with either a soft MCU on-chip or an external MCU, the flash memory offers an excellent code space solution with the ability to execute in place, eliminating the need to shadow code in RAM. Increasing overall data reliability, the flash memory integrates error correction circuitry (ECC) with single-bit error-fix and two-bit error-detect capabilities.
- Advanced I/O Standards
- 700 Mbps LVDS-, BLVDS-, and MLVDS-capable DDR I/Os
- Multiple I/O banks per device
- Single-ended I/O standards: LVTTL, LVCMOS 3.3 V /2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, andLVCMOS 2.5 V / 5.0 V input
- Differential I/O standards: LVPECL, LVDS, BLVDS,and MLVDS
- Voltage-referenced I/O standards
- Registered I/Os
- Hot-swap-compliant I/Os
- Charge Pumps:Fusion devices are designed to operate from a single 3.3 V supply. The Fusion devices supply all other voltages to write (program) the embedded flash memory and the FPGA core.
- Analog Quads:Leveraging its high-voltage flash process, Fusion analog I/Os support direct connection from as low as –10.5 V up to +12 V. By eliminating the need for external components to scale down (or up) signals before and after processing, Fusion reduces cost, component count, and board space, while increasing reliability and ease of use. Differential current and temperature monitor blocks with integrated amplifiers increase accuracy and efficiency.
- Flash FPGA VersaTile:The programmable logic VersaTile elements of Fusion allow synthesis and mapping tools to use any tile as a three-input lookup table equivalent, a D-flip-flop, or latch (with or without enable). Fusion devices with VersaTiles offer an abundance of registers, so you can often choose a smaller device and still meet register requirements.
- SRAM and FIFOs:Fusion devices have embedded dual-port SRAM and FIFO blocks along the north and south sides of the device. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. Dedicated FIFO control logic enables flexible and efficient FIFO implementations.
- Integrated Oscillators — Crystal and RC:Fusion includes a complete collection of clocking resources: crystal oscillator circuit, 1% RC oscillator, RTC, NGMUX, and phase-locked loops (PLLs). Fusion devices can generate, multiply, divide, phase shift, and distribute clock signals for both on-chip and off-chip use, eliminating the need for external clock sources.
- Routing Structure:Fusion provides millions of flash cell switches and an abundance of hierarchical routing resources, enabling extensive design and routing flexibility. VersaNet (segmented global) routing allows high-fanout nets to traverse small or large areas of the Fusion devices with flexibility and low skew. The VersaNet network is used automatically by the software tools to route clocks and high-fanout nets.
- JTAG:Fusion devices use industry standard JTAG programming (IEEE 1532). In addition, Fusion devices support board-level JTAG (IEEE 1149) I/O boundary scan.
Product Tables
Product Family
Please refer to the ordering tab for a list of all available part numbers.
| Fusion Devices | AFS0909 | AFS250 | AFS6007 | AFS15007 |
|---|---|---|---|---|
| ARM Cortex-M11 Devices | AFS250 | M1AFS600 | M1AFS1500 | |
| Pigeon Point Devices 2 | P1AFS600 5 | P1AFS1500 5 | ||
| MicroBlade Devices 2 | U1AFS250 3 | U1AFS600 3 | U1AFS1500 3 | |
| General | ||||
| System Gates | 90,000 | 250,000 | 600,000 | 1,500,000 |
| Equivalent LEs | 900 | 3K | 7K | 16K |
| Tiles (D-flip-flops) | 2,304 | 6,144 | 13,824 | 38,400 |
| Secure (AES) ISP | Yes | Yes | Yes | Yes |
| PLLs | 1 | 1 | 2 | 2 |
| Globals | 18 | 18 | 18 | 18 |
| Memory | ||||
| Flash Memory Blocks (2 Mbits) | 1 | 1 | 2 | 4 |
| Total Flash Memory Bits | 2M | 2M | 4M | 8M |
| FlashROM Bits | 1,024 | 1,024 | 1,024 | 1,024 |
| RAM Blocks (4,608 bits) | 6 | 8 | 24 | 60 |
| RAM (kbits) | 27 | 36 | 108 | 270 |
| Analog and I/Os | ||||
| Analog Quads | 5 | 6 | 10 | 10 |
| Analog Input Channels | 15 | 18 | 30 | 30 |
| Gate Driver Outputs | 5 | 6 | 10 | 10 |
| I/O Banks (+ JTAG) | 4 | 4 | 5 | 5 |
| Maximum Digital I/Os | 75 | 114 | 172 | 252 / 223 (K Temp) |
| Analog I/Os | 20 | 24 | 40 | 40 |
| Temperature Grades | C, I | C, I | C, I, K 4 | C, I, K 4 |
| I/Os: Single-/Double-Ended (Analog) | ||||
| QN1088 | 37/9 (16) | |||
| QN1808 | 60/16 (20) | 65/15 (24) | ||
| FG256 | 114/37 (24) | 119/58 (40) | 119/58 (40) | |
| FG484 | 172/86 (40) | 223/109 (40) | ||
| FG676 | 252/126 (40) | |||
Notes:
- Refer to the Cortex-M1 product brief for more information.
- MicroBlade and Pigeon Point devices are not offered on extended temp range.
- MicroBlade devices are only offered in FG256.
- Extended Military temperature range supported from -55C to 100C
- Pigeon Point devices are only offered in FG484 and FG256
- Fusion devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600)
- Extended temperature supported devices
- Package not available
- AFS090 is not available.
- For Part availability please refer to PDN and EOL notifications.
Documents
Microsemi content is being moved to microchip.com. We will post new documents and downloads on microchip.com. Please visit our documentation landing page on microchip.com to access the latest documentation and downloads. The link will take you to a landing page where you can navigate to the product you are looking for. If you have any further questions, please reach out to FPGA_marketing@microchip.com
Datasheets User's Guides & Manuals Application Notes Application Briefs Tutorials White Papers
| Extended Temperature Fusion Family | 16 MB | 2/2013 |
| DS0092: Fusion Mixed-Signal FPGAs Datasheet | 9.34 MB | 5/2018 |
Developing an Application on Core8051s IP-Based Embedded Processor System Using Firmware Catalog Drivers User's Guide
|
1 MB | 8/2012 |
Fusion and Extended Temperature Fusion FPGA Fabric User's Guide
|
28 MB | 9/2012 |
| Fusion Starter Kit Quick Start Guide | 292 KB | 3/2012 |
| SmartGen Cores Reference Guide for Software v11.0 | 3 MB | 4/2013 |
Fusion Webserver Demo Using uIP and FreeRTOS
|
1 MB | 2/2012 |
| DC-DC Regulator Guide for Microsemi FPGAs and SOC FPGAs | 379 KB | 3/2013 |
| TU0308: ARM Cortex-M1 Embedded Processor Tutorial |
3.5 MB | 6/2017 |
Design Resources
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Product Selector Guide
Fusion mixed signal FPGAs integrate configurable analog, large flash memory blocks, comprehensive clock generation and management circuitry, and high-performance, flash-based programmable logic in a monolithic device. Microsemi's innovative Fusion FPGA architecture can be used with the Microsemi soft microcontroller (MCU) core as well as the performance-maximized 32-bit ARM Cortex-M1 Processor. Fusion devices are the world's first mixed signal FPGA platform. In addition to supporting commercial and industrial temperature devices, Microsemi offers Fusion FPGAs with specialized screening for extended temperature applications.
