IGLOO

Overview

The Industry's Low-Power FPGAs

The IGLOO® series of ultra-low density FPGAs includes IGLOO/e, IGLOO nano and IGLOO PLUS —the industry's low-power FPGAs. IGLOO FPGA family are designed to meet the demand of low power and small foot print requirements of today's portable and power-conscious electronics.

The IGLOO low-power FPGA family support up to 35K logic elements with up to 504 kbits of true dual-port SRAM, up to 6 embedded PLLs, and up to 620 user I/Os. Low-power applications that require 32-bit processing can use the ARM ® Cortex-M1 processor without license fee or royalties in M1 IGLOO devices.

The IGLOO FPGA family devices are available in small footprint (3x3, 4x4, 5x5, 6x6 and 8x8 mm), high
density, chip-scale and quad flat no-lead packages.

The IGLOO series includes:

Device Comparison

IGLOO Family	IGLOO/e	IGLOO nano	IGLOO PLUS
ARM - Enabled	M1 IGLOO/e
Overview	The low-power programmable solution	The industry's lowest-power, smallest-size solution	The low-power FPGA with more I/O per LE compared to IGLOO
Equivalent LEs	330-35K	100-3K	330-1K
Max User I/Os	341	71	212
Power Consumption	5 µW	2 µW	5 µW

Flash*Freeze Technology

The Flash*Freeze technology used in IGLOO devices enables easy entry and exit from low power mode which consumes as little as 2 µW, while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management without a need to turn off voltages, I/Os, or clocks at the system level.In Flash*Freeze mode, power drops to as low as 2 µW, and no additional components are required to turn off I/Os or clocks while preserving the design information, SRAM content, and registers. I/Os can maintain their state during Flash*Freeze mode. Entering and exiting Flash*Freeze mode takes less than 1 µs.

Small Footprint Packages

IGLOO FPGAs are true single-chip devices, do not require configuration or other support components, and offer a variety of small-footprint packages with high I/O pin count to match design needs.The IGLOO family is offered in a small form factor (3x3, 4x4, 5x5, 6x6, and 8x8 mm), high-density, chip-scale packages and quad flat no-lead packages.

IGLOO/e

The IGLOO/e family of low-power flash FPGAs, based on a 130-nm flash process, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features.

The Flash*Freeze technology used in IGLOO/e devices enables entering and exiting an ultra-low power mode while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode.

IGLOO/e devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on 6 integrated phase-locked loops (PLLs). IGLOO/e devices have up to 35K LEs, supported with up to 504 kbits of true dual-port SRAM and up to 620 user I/Os.
M1 IGLOO/e devices support the high-performance, 32-bit ARM® - Cortex-M1™ Processor developed by ARM for implementation in FPGAs. Cortex-M1 is available for free from Microsemi for use in M1 IGLOO/e FPGAs.

The IGLOO family includes:

IGLOO
M1 IGLOO : ARM® - Cortex-M1 enabled IGLOO devices

The IGLOOe family includes:

IGLOOe
M1 IGLOOe : ARM® - Cortex-M1 enabled IGLOOe devices

Key Features

Low power in Flash*Freeze mode
Best system performance of 250 MHz
Low power active capability
Small footprint packages
Reprogrammable flash technology
1.2 V to 1.5 V operation
High-capacity, advanced I/Os
Clock conditioning circuits (CCCs) and PLLs
Embedded SRAM and nonvolatile memory (NVM)
In-system programming (ISP) and security

Product Family

Please refer to the ordering tab for a list of all available part numbers.

IGLOO Devices	AGL030	AGL060	AGL125	AGL250	AGL400	AGL600	AGL1000	AGLE600	AGLE3000
Cortex-M1 Devices				M1AGL250		M1AGL600	M1AGL1000		M1AGLE3000
System Gates	30,000	60,000	125,000	250,000	400,000	600,000	1,000,000	600,00	3,000,000
Equivalent LEs	330	700	1.5 K	3K	5K	7K	11K	7K	35K
Quiescent Current (typical)in Flash*Freeze Mode( µW)	5	10	16	24	32	36	53	49	137
RAM kbits (1,024 bits)		18	36	36	54	108	144	108	504
4,608-Bit Blocks		4	8	8	12	24	32	24	112
FlashROM Bits	1,024	1,024	1,024	1,024	1,024	1,024	1,024	1024	1024
Secure (AES) ISP¹		Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
Integrated PLLs in CCCs²		1	1	1	1	1	1	6	6
I/O Standards	Std., Hot-Swap	Std.+	Std.+	Std.+/ LVDS	Std.+/ LVDS	Std.+/ LVDS	Std.+/ LVDS	Pro	Pro
I/O Banks (+JTAG)	2	2	2	4	4	4	4	8	8
Maximum User I/Os	77	71	133	143	178	215	300	165	341
Speed Grades	Std.	Std.	Std.	Std.	Std.	Std.	Std.	Std.	Std.
Temperature Grades	C, I	C, I	C, I	C, I	C, I	C, I	C, I	C,I	C,I

Notes:

AES is not available for ARM-enabled IGLOO devices.
AGL060 in CS121 does not support the PLL.

Packing and I/Os

IGLOO Devices	AGL030	AGL060	AGL125	AGL250	AGL400	AGL600	AGL1000	AGLE600	AGLE3000
Cortex-M1 Devices				M1AGL250		M1AGL600	M1AGL1000		M1AGLE3000
QN48	34
UC81	66
CS81	66
CS121			96
VQ100	77	71	71	68/13
CS196			133	143/35³	143/35
FG144			97	97/24		97/25	97/25
FG256²					178/38	177/43	177/44	165/79
CS281						215/53	215/53
FG484²							300/74		341/168

Notes:

Each used differential I/O pair reduces the number of single-ended I/Os available by two.
FG256 and FG484 are footprint-compatible packages.
The M1AGL250 device does not support CS196 package.
For AGLE3000 devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank
When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os).
When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one.
"G" indicates RoHS-compliant packages. See Ordering Information

Documents

Datasheets User's Guides & Manuals Application Notes Application Briefs Tutorials
White Papers Product Information Brochures (PIB) Other Information

Datasheets

DS0095: IGLOO Low Power Flash FPGAs Datasheet		5.8 MB	5/2016
IGLOOe Low-Power Flash FPGAs Datasheet		8 MB	12/2012

IGLOO Pin Assignment Tables	IGLOOe Pin Assignment Tables
IGLOO QN48 Pinouts(ZIP,7/2014) IGLOO QN68 Pinouts(ZIP,7/2014) IGLOO CS81 Pinouts(ZIP,7/2014) IGLOO VQ100 Pinouts(ZIP,7/2014) IGLOO CS121 Pinouts(ZIP,7/2014) IGLOO FG144 Pinouts(ZIP,7/2014) IGLOO CS196 Pinouts(ZIP,7/2014) IGLOO CQ208 Pinouts(ZIP,7/2014) IGLOO FG256 Pinouts(ZIP,7/2014) IGLOO CS281 Pinouts(ZIP,7/2014) IGLOO CS284 Pinouts(ZIP,7/2014) IGLOO FG484 Pinouts(ZIP,7/2014)	IGLOOe FG256 Pinouts(ZIP,7/2014) IGLOOe FG484 Pinouts(ZIP,7/2014) IGLOOe FG896 Pinouts (ZIP,7/2014)

User's Guides and Manuals

IGLOO FPGA Fabric User's Guide	21 MB	9/2012
IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide for Software v10.1	1 MB	11/2012
IGLOOe FPGA Fabric User's Guide	21 MB	9/2012
DC-DC Regulator Guide for Microsemi FPGAs and SOC FPGAs	379 KB	3/2013

Application Notes

AC215: Using IGLOO and ProASIC3 FIFO for Generating Periodic Waveforms App Note	614 KB	08/2015
AC222: Using Fusion, IGLOO, and ProASIC3 RAM as Multipliers App Note	853 KB	08/2015
AC246: Level Shifter Design Example App Note Design Files (ZIP, 15 KB, 04/09)	350 KB	4/2009
AC257: Microcontroller I/O Expander Design Example App Note Design Files (ZIP, 1.8 MB, 04/09)	762 KB	4/2009
AC265: Clock Generation and Distribution Design Example App Note Design Files (ZIP, 192 KB, 04/09)	592 KB	11/2012
AC268: Using IGLOO and ProASIC3 FPGAs as a System Power Sequencer Design Example App Note Design Files (ZIP, 3 MB, 04/09)	981 KB	08/2015
AC269: Implementing an OLED Controller Parallel Interface Design Example App Note Design Files (ZIP, 609 KB, 04/09)	841 KB	08/2015
AC311: Physical Interface to QDRII Memories using Microsemi ProASIC3E FPGAs App Note	522 KB	1/2008
AC323: Dynamic Power Reduction in Flash FPGAs App Note	2 MB	10/2012
AC324: SPI-to-I2C Interface App Note Design Files (ZIP, 2.4 MB, 04/09)	615 KB	4/2009
AC326: GPIO Expansion Using UART Design Example App Note Design Files (ZIP, 4.9 MB, 04/09)	501 KB	4/2009
AC327: UART-to-SPI Interface Design Example App Note Design Files (ZIP, 375 KB, 04/09)	738 KB	10/2012
AC328: NAND Flash Interface Design Example App Note Design Files (ZIP, 2.5 MB, 06/09)	679 KB	6/2009
AC329: Mobile SDRAM Interface Design Example App Note Design Files (ZIP, 587 KB, 06/09)	587 KB	6/2009
AC330: Smart Card Interface Design Example App Note Design Files (ZIP, 3.6 MB, 06/09)	1 MB	6/2009
AC331: Flash*Freeze Control Using JTAG App Note Design Files (ZIP, 21 KB, 06/09)	298 KB	6/2009
AC332: Flash*Freeze Control Using an Internal Oscillator App Note	460 KB	6/2009
AC349: Bidirectional Level Shifter App Note Design Files (ZIP, 2.1 KB, 2/11)	396 KB	4/2011
AC373: Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note Design Files (ZIP, 5.1 MB, 11/11)	2 MB	11/2011
AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based FPGAs and SoC FPGAs App Note	2 MB	9/2011
AC379: Advanced Static Timing Analysis Using SmartTime App Note	6 MB	11/2011
AC380: Internal Power-on Reset and Post Programming Reset Circuit for Flash-Based FPGAs App Note Design Files (RAR, 10.9 MB, 11/12)	541 KB	2/2012
AC382: Zeroization App note Design Files (RAR, 14.8 MB, 11/12) Programming Files (RAR, 177 KB, 5/12)	597 KB	3/2012
Designing for Performance on Flash-Based FPGAs	764 KB	3/2008
HB: Power-Up/-Down Behavior of Low-Power Flash Devices (v1.2)	686 KB	12/2011

Application Briefs

AC242: Intelligent Mixed Signal FPGAs in Portable Medical Devices App Brief	568 KB	8/2012
AC290: Trainable Image Recognition System Using Low Power Flash FPGAs App Brief	167 KB	11/2006
AC293: System Power Optimization Controller Using IGLOO FPGAs App Brief	99 KB	12/2006
AC357: FlashPro4 Backward Compatibility with FlashPro3 App Brief	448 KB	10/2012
AC368: FPGA Solutions for Defibrillators App Brief	559 KB	7/2011
AC369: FPGA Solutions for Ultrasound App Brief	433 KB	7/2011
AC370: FPGA Solutions for 4D Imaging-based Therapy App Brief	483 KB	7/2011
AC371: Personal Heart Monitor App Brief	486 KB	7/2011
Low Power IDE Data Storage Solution	38 KB	10/2006

Tutorials

TU0308: ARM Cortex-M1 Embedded Processor Tutorial

3.51 MB

6/2017

Quality & Reliability Reports

Microsemi SoC Reliability Report - Rev. 11

3 MB

5/2013

White Papers

Competitive Programmable Logic Power Comparison White Paper	1 MB	4/2008
Developing Embedded Applications with ARM Cortex-M1 Processors in Microsemi IGLOO and Fusion FPGAs White Paper	548 KB	3/2009
FPGA Reliability and the Sunspot Cycle White Paper		9/2011
Incredible Shrinking Medical Devices White Paper	316 KB	10/2008
Power-Aware FPGA Design White Paper	1 MB	2/2009
Putting Low Power and Flexibility Where It Matters Most: Handheld Portable Applications White Paper		8/2012
Reducing System Power White Paper	33 KB	8/2006
Secure Foundations White Paper		12/2010
Single-Event Upsets (SEUs) and Medical Devices White Paper		12/2010
Size, Reliability and Security: The Essential Ingredients for Medical Devices White Paper		8/2011
The Many Flavors of Low-Power, Low-Cost FPGAs White Paper	517 KB	4/2008
The New "Power-Smart" Power Paradigm White Paper	210 KB	7/2007

Product Information Brochures (PIB)

Microsemi Photovoltaic Solutions Brochure		2 MB	6/2012
IGLOO Low-Power Flash FPGAs Brochure		2 MB	11/2013

Other Information

Power FAQs

49 KB

8/2006

Design Resources

Design Software	Libero SoC Design Software integrates industry leading synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and push button design flow.
Request a License	Free full feature licenses are available for all family members.
Packaging	Microsemi Packaging Resources and Information
Design Hardware	IGLOOe devices are supported by design hardware supplied by Microsemi and partners. Microsemi's IGLOO Icicle Evaluation Kit, based on the 5-µW IGLOO FPGA, is a low-cost, portable, low-power demonstration platform. The Icicle evaluation board enables you to measure power consumption (dynamic, static and Flash*Freeze) with the core operating at either 1.2 V or 1.5 V.
Programming & Debug	IGLOO FPGAs are supported by FlashPro for in circuit programming and Silicon Sculptor 3 for standalone device programming.
IP Cores	Search for IGLOO IP cores
Embedded Ecosystem	The IGLOO Embedded Ecosystem includes a number of partners who provide third party tools, firmware and middleware.
Partners	Many of Microsemi’s Partners are engaged in development with IGLOO devices
Power Analysis	Leverage our Excel based IGLOO power calculator to evaluate power for your design without running through the full design flow. SmartPower can also provide design specific power analysis for your design implementation within Libero.
IBIS Models	Generic IGLOO/e IBIS Models are available for signal integrity simulations. Design specific files can also be exported from your design implementation in Libero.
BSDL Models	Generic IGLOO/e BSDL Models are available for boundary scan testing. Design specific files can also be exported from your design implementation in Libero.

IGLOO nano

Microsemi's IGLOO® nano low-power FPGAs offer groundbreaking possibilities in power, size and operating temperature. Available in logic densities from 100 LEs to 3K LEs, the 1.2 V to 1.5 V IGLOO nano devices have been designed for high-volume applications where power and size are key decision criteria.