Course Descriptions
Overview
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RISC-V for PolarFire is a 1-day course for engineers who are implementing RISC-V designs targeting Microchip's PolarFire FPGAs. The class introduces the RISC-V ISA, Microchip's RISC-V offerings and the RISC-V Ecosystem. The class describes on how to implement and debug RISC-V designs. Hands-on lab exercises targeting the PolarFire Splash kit are included to provide practical applications of the material presented.
This class is held at Microchip's N. 1st Street facility in San Jose, CA. Students who are unable to travel to San Jose can attend remotely via the web.
Course Objectives:
- Implement a RISC-V design targeting the PolarFire FPGA family
- Develop and debug firmware applications using Microchip's free SoftConsole software development environment
Course Requirements:
- Familiarity with the FPGA design flow and microprocessor code development
- Familiarity with the Microchip PolarFire FPGA family
- Familiarity with the Microchip Libero SoC toolset
Libero SoC training is a 2-day course consisting of lectures and hands-on labs describing the steps to implement a PolarFire, IGLOO®2 or SmartyFusion®2 SoC FPGA design using the Libero SoC toolset. Each student will use Libero SoC to take a design from conception to a functioning FPGA. The class labs target Microchip PolarFire Splash kit or the PolarFire Evaluation kit. Hands-on labs can be implemented using VHDL or Verilog. This class is held at the Microchip's N .1st Street facility in San Jose, CA. Students can also attend remotely.
Course Objectives:
- Project creation with the Libero SoC
- HDL entry using the Libero SoC HDL Editor
- Using PolarFire core generators and SmartDesign
- Testbench generation and simulation using the ModelSim ME Pro Simulator
- Libero SoC Enhanced Constraint Flow
- Synthesizing with Synplify Pro ME
- Using the I/O Editor to make pin assignments and set I/O attributes
- Floorplanning with ChipPlanner
- Design layout (place-and-route)
- Static timing analysis with SmartTime
- Power Analysis with SmartPower
- Generation of back-annotated timing files and programming files
- FPGA programming
- Debugging with SmartDebug and Identify ME
Course Requirements:
- Experience with PCs and Windows operating system
Designing with SmartFusion®2 SoC FPGAs Back to Top
Designing with SmartFusion2 SoC FPGAs is two 1-day classes for FPGA designers, embedded designers and firmware engineers who are designing with Microchip's SmartFusion2 SoC family. These classes describe the SmartFusion2 architecture, including the microcontroller subsystem (MSS) and FPGA fabric along with the software tools and design flows for implementing SmartFusion2 designs. Hands-on lab exercises targeting one of the SmartFusion2 kits are included to provide practical applications of the material presented. Students may attend one or both days of training. These classes are held at the Microchip facility on N. 1st Street in San Jose, CA. Students can also attend remotely.
Course Objectives:
- Develop an understanding of the SmartFusion2 architecture
- Develop an understanding of the SmartFusion2 design flow to quickly implement SmartFusion2 applications
Course Requirements:
- Experience with PCs, Windows operating system, Microchip Libero SoC toolset and software development tools, such as SoftConsole, Keil or IAR, are recommended.
Course Outline:
- Day 1: SmartFusion2 FPGA Fabric
- FPGA fabric resources
- Math blocks
- Clocking and global resources
- SmartFusion2 I/Os
- Math block design techniques
- Hands-on labs
- Day 2: SmartFusion2 Microcontroller Subsystem
- Cortex-M3 microcontroller subsystem
- Instruction cache
- Debug features (SWV, ETM)
- SmartFusion2 AHB bus matrix
- Peripherals
- SmartFusion2 eSRAM and eNVM
- SmartFusion2 DDR bridge
- SmartFusion2 Fabric interface
- System Builder / SmartDesign MSS configurator
- Firmware drivers and sample projects for SoftConsole, Keil and IAR toolchains
- Adding user logic in SmartFusion2 designs
- Hands-on labs
Introduction to PolarFire is a 1-day course for engineers who are implementing designs targeting Microchip's PolarFire FPGAs. This class describes the PolarFire FPGA architecture, including the logic element, RAM blocks, Math blocks, uPROM, clocking resources and I/Os. The PolarFire high speed serial interfaces and unique debug features are introduced. Hands-on lab exercises targeting the PolarFire Splash kit or the PolarFire Evaluation kit are included to provide practical applications of the material presented. This class is held at Microchip's facility on N. 1st Street in San Jose, CA. Students who are unable to travel to San Jose can attend remotely via the web.
Course Objectives:
- Develop an understanding of the PolarFire FPGA family architecture details and how to implement designs using these features
- Become familiar with the Libero SoC design flow to implement PolarFire designs
Course Requirements:
- Familiarity with digital logic design and basic FPGA design flow
- Familiarity with Microchip Libero SoC toolset
This course is a 1-day training course that builds on the concepts introduced in the Introduction to PolarFire FPGAs training class. The focus is on using the PolarFire IOs to implement high-speed serial interfaces and source-synchronous designs. Hands-on lab exercises targeting the PolarFire Evaluation kit are included to provide practical applications of the material presented.
This class is held at Microchip's facility on N. 1st Street in San Jose, CA. Students who are unable to travel to San Jose can attend remotely via the web.
Course Objectives:
- Develop an understanding the PolarFire IO features that support serial interfaces.
- Learn how to use the IO configurators to implement source synchronous interfaces.
Course Requirements:
- Familiarity with the PolarFire FPGA architecture. Engineers who are not familiar with the PolarFire FPGA family should attend the Introduction to PolarFire training class.
- Familiarity with source synchronous designs.
- Familiarity with the Microchip Libero SoC toolset.
Introduction to PolarFire SoC is a 1-day course for engineers who are implementing designs targeting Microchip's PolarFire SoC FPGAs. This class describes the PolarFire SoC FPGA architecture, including the five-core Linux® capable processor subsystem based on the RISC-V ISA, the Flexible L2 memory subsystem and the embedded peripherals. The course also describes the PolarFire SoC design flow. Hands-on lab exercises are included to provide practical applications of the material presented. This class is held at Microchip's facility on N. 1st Street in San Jose, CA. Students who are unable to travel to San Jose can attend remotely via the web.
Course Objectives:
- Develop an understanding of the PolarFire SoC FPGA family architecture details and how to implement designs.
- Become familiar with the Libero SoC design flow to implement PolarFire SoC designs.
Course Requirements:
- Familiarity with the PolarFire FPGA architecture. Engineers who are not familiar with the PolarFire FPGA family should attend the Introduction to PolarFire training class.
- Familiarity with the FPGA design flow and microprocessor code development.
- Familiarity with the Microchip Libero SoC toolset.
