Low Power Leadership
Overview
Optimized for the Lowest Total Power
Microchip FPGAs and SoC FPGAs consume 30% to 50% lower total power than competitive FPGAs. This is enabled by the use of non-volatile technology, which yields inherently low leakage between configuration cells. Non-volatile technology means Microchip FPGAs are instant on at power-up, resulting in no in-rush current and zero configuration current.
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| Total System Power Profile | ||
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| SRAM FPGAs | Microsemi FPGAs | |
| In-Rush Power (during power up) | High | Zero |
| Configuration Power | High | Zero |
| Static Power | High | Ultra Low |
| Dynamic Power | High | Low |
| Low Power Modes | Low | Ultra Low |
| Total Power | High | Lowest Power |
No In Rush and Configuration Current
SRAM FPGAs power up in an unconfigured state and need to complete the initial power-up and reset sequence. Initially, the various configuration bits are in unknown states and need to initialize on every power cycle. Hence, a current surge is created that may generate a spike as high as several amperes for as long as a few hundred microseconds resulting in an In-rush power. To mitigate this current spike, many SRAM FPGAs have added complex power sequencing requirements to the system, adding component cost and board space.
In addition to the initial in-rush power, each time an SRAM FPGA powers up a configuration cycle is required, which burns additional power as well as delaying start up of FPGA functionality every time the device is power cycled.
Industry’s Lowest Static Power
Unlike SRAM cells used in competitors FPGAs, which are typically built using six transistors, our Flash based configuration cells (IGLOO2 example shown) are built using a single transistor, translating into exponentially lower leakage current versus SRAM cells.
Typical SRAM Cell |
Non-volatile Cell |
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Power Comparisons
Mid-Range FPGAs Up to 500K Logic Elements
Microsemi's PolarFire FPGAs have significantly lower static power and transceiver power than competing SRAM FPGAs, resulting in up to 50% lower total power.
PolarFire FPGA Power Comparison - Communications Examples
Low-Density FPGAs
Microsemi's SmartFusion2 SoC FPGAs have 10x lower static power, 5x lower transceiver power and 50% lower total power than competing SRAM SoC FPGAs. Comparison is shown below:
Microsemi's IGLOO2 FPGAs have 3x lower static power, 5x lower transceiver power and 25% lower total power than competing SRAM FPGAs. Comparison is shown below:
Minimizing Dynamic Power Consumption in SmartFusion2 and IGLOO2 Devices
Customers can enjoy lower dynamic power through:
- Best in class 5G transceiver power: power per Gbps for each SERDES lane is as low as 13mW, which is upto 5X lower when compared to other cost optimized FPGAs with similar capabilities
- More hard IP and resources in smaller devices: IGLOO2 and SmartFusion2 provide more I/O, more transceivers, more PCI Express Endpoints and a unique high performance memory subsystem to provide more capabilities in smaller and low power devices
- Unlike our competitors, Mirosemi has chosen to embed a processor subsystem that has inherently lower power. The embedded ARM Cortex-M3 subsystem has multiple low power modes including a Sleep Mode and a Deep Sleep mode
- We also provide ways for the user to optimize designs for lower power using various tools to compute power profiles, smart floor planning and power optimized place and route. Details are provided in AC323
Resources
PolarFire Low Power Resources
SmartFusion2 and IGLOO2 Low Power Resources
Power Estimation
Early power estimation helps designers to define the architecture within the power budget by applying power-saving strategies. It also helps the board designers to design and select the power supplies and heat sink. The Power Estimator workbook enables you to estimate power consumption from early design concept to design implementation. It also provides details about thermal analysis and factors that contribute to power consumption. Device resources, operating frequency, clock resources, toggle rates, and many other parameters are entered into the Power Estimator workbook. These parameters are then combined with the power models to estimate the power. The power models are based on simulation or characterized device data.
| PolarFire SoC Power Estimator | 01/2021 |
| UG0897: PolarFire SoC FPGA Power Estimator User Guide |
5/2021 |
| SmartFusion2 and IGLOO2 Power Calculator |
1/2016 |
| SmartFusion2 and IGLOO2 Power Calculator User's Guide | 8/2014 |
| RTG4 Power Estimator | 06/2021 |
| RTG4 Power Estimator User Guide | 1/2015 |
| IGLOO Power Calculator (applicable to IGLOO, IGLOOe, and IGLOO nano) |
6/2011 |
| ProASIC3 Power Calculator (applicable to ProASIC3, ProASIC3E, ProASIC3 nano, ProASIC3L, and RT ProASIC3) |
6/2015 |
| SmartFusion Power Calculator | 9/2011 |
Additional Power Estimators and Calculators for other Microsemi FPGAs
