Low Power FPGAs
Overview
Power-optimized FPGAs
Microsemi recently announced PolarFire cost-optimized FPGAs that deliver the lowest power at mid-range densities. PolarFire FPGAs deliver up to 50% lower power than equivalent SRAM FPGAs. During the design of the PolarFire family Microsemi specifically focused on power-optimized design choices to result in the lowest power mid-range FPGAs, to continue Micorsemi's leadership in low power for low-density and CPLD replacement devices.
These efforts result in the power numbers are shown below for PolarFire FPGAs:
- Low device static power—34 mW for 100K LE device
- Low power transceiver lane—90 mW at 10G
| Characteristics | Microsemi PolarFire Devices | Competitors |
|---|---|---|
| Static Power | Non-volatile process yields very low static power | SRAM static power is very high, even with exotic process technologies |
| Inrush Power | Negligible | High consumption of current when SRAM is initializing |
| Transceiver Power | Optimized for 12.7 Gbps which yields the lowest power | Transceiver designed to support 28 Gbps. Power hungry for lower speeds. |
| Integrated Hard IP | DDR & SGMII PHY, PCIe endpoint/root port, cryptoprocessor | Crypto processors & SGMII only available in high end devices |
| Total Power (Static + Dynamic) | Up to 50% lower power | High |
PolarFire FPGAs also offer a variety of techniques and capabilities to lower the total application power. Users can take advantage of these features to lower both capital and operational expenditures with smaller or no heat sinks, smaller or fewer fans, lower cooling costs, and so on. Additionally, the lower total power advantage can also allow the user to pack more compute operations into an existing thermal budget.
Microsemi Low Power FPGAs and SoC FPGAs
Microsemi FPGAs and SoC FPGAs have dramatically lower total power than competitive FPGAs. This is enabled by the inherent low leakage of Microsemi’s Flash-based architectures as well as no in-rush, zero-configuration current and Microsemi devices' Flash*Freeze capability enables even lower power operation for low duty cycle applications.
| Total System Power Profile | ||
|---|---|---|
| SRAM FPGAs | Microsemi FPGAs | |
| In-Rush Power (during power up) | High | Zero |
| Configuration Power | High | Zero |
| Static Power | High | Ultra Low |
| Dynamic Power | High | Low |
| Low Power Modes | Low | Ultra Low |
| Total Power | High | Lowest Power |
Microsemi FPGA families include important low power features:
- No in-rush and configuration current
- Industry’s lowest power transceivers
- Industry’s lowest static power
- Flash*Freeze ultra low standby mode
- ARM Cortex-M3 low power modes (SmartFusion2)
- SoC peripheral low power modes (SmartFusion2)
No In Rush and Configuration Current
SRAM FPGAs power up in an unconfigured state and need to complete the initial power-up and reset sequence. Initially, the various configuration bits are in unknown states and need to initialize on every power cycle. Hence, a current surge is created that may generate a spike as high as several amperes for as long as a few hundred microseconds resulting in an In-rush power. To mitigate this current spike, many SRAM FPGAs have added complex power sequencing requirements to the system.
In addition to the initial in-rush power, each time an SRAM FPGA powers up a configuration cycle is required, which burns additional power as well as delaying start up of FPGA functionality everytime the device is power cycled.
As Microsemi FPGA are non-volatile and do not need external configuration devices for reprogrammability, Microsemi Flash FPGA eliminates hundreds of milliwatts at device startup and configuration and eliminate the need for external devices for mitigation.
Industry’s Lowest Static Power
Unlike SRAM cells used in competitors FPGAs, which are typically built using six transistors, our Flash based configuration cells (IGLOO2 example shown) are built using a single transistor, translating into exponentially lower leakage current versus SRAM cells.
Power Comparison
Mid-Range FPGAs Up to 500K Logic Elements
Microsemi's PolarFire FPGAs have significantly lower static power and transceiver power than competing SRAM FPGAs, resulting in up to 50% lower total power.
PolarFire FPGA Power Comparison - Communications Examples
Low-Density FPGAs
Microsemi's SmartFusion2 SoC FPGAs have 10x lower static power, 5x lower transceiver power and 50% lower total power than competing SRAM SoC FPGAs. Comparison is shown below:
Microsemi's IGLOO2 FPGAs have 3x lower static power, 5x lower transceiver power and 25% lower total power than competing SRAM FPGAs. Comparison is shown below:
Minimizing Dynamic Power Consumption in SmartFusion2 and IGLOO2 Devices
Customers can enjoy lower dynamic power through:
- Best in class 5G transceiver power: power per Gbps for each SERDES lane is as low as 13mW, which is upto 5X lower when compared to other cost optimized FPGAs with similar capabilities
- More hard IP and resources in smaller devices: IGLOO2 and SmartFusion2 provide more I/O, more transceivers, more PCI Express Endpoints and a unique high performance memory subsystem to provide more capabilities in smaller and low power devices
- Unlike our competitors, Mirosemi has chosen to embed a processor subsystem that has inherently lower power. The embedded ARM Cortex-M3 subsystem has multiple low power modes including a Sleep Mode and a Deep Sleep mode
- We also provide ways for the user to optimize designs for lower power using various tools to compute power profiles, smart floor planning and power optimized place and route. Details are provided in AC323
Flash*Freeze
Flash*Freeze Mode
In systems that operate reactively or periodically, PolarFire, SmartFusion2 and IGLOO2 devices can dramatically reduce power. Saving energy in periodic and reactive systems is achieved by moving into a very low power state when processing is not necessary, this mode is called Flash*Freeze and is unique to Microsemi FPGAs.
SmartFusion2 SoC FPGAs can use the ARM Cortex-M3 low power modes and Flash*Freeze low power more for the FPGA fabric and I/Os and IGLOO2 FPGAs can enter Flash*Freeze with external I/O control.
Figure 1: Example system moving from Flash Freeze to Regular Operation and back to Flash Freeze
Flash*Freeze enables the rapid stopping and starting of the FPGA fabric and related I/Os while preserving the state of the FPGA fabric and dramatically reducing power. While in Flash*Freeze, the state of the FPGA is maintained so that upon exit from Flash*Freeze, the device continues to operate from where it left off.
Applications of Flash*Freeze
- Communications
In low power communication systems, power is reduced by using periodic bursts of communication. This eliminates the constant power in the amplifiers and the rest of the system. - Sensor Networks
Sensor networks include both low power communications and active sensors to perform distributed measurements. The active sensors may be turned on periodically (Traffic image, weather sensor) or turn on in response to an event (Earthquake). After the measurement has been taken, the information is uploaded as an information burst and then the equipment goes back to sleep – Flash*Freeze. - Medical Equipment
Many types of medical equipment is used for monitoring patient health. These types of systems have relatively low sampling rates and can therefore utilize periodic operation as a means to minimize power consumption. This is especially useful in portable medical equipment.
Resources
PolarFire Low Power Resources
SmartFusion2 and IGLOO2 Low Power Resources
Power Estimation
Early power estimation helps designers to define the architecture within the power budget by applying power saving strategies. It also helps the board designers to design and select the power supplies and heat sink. The Power Estimator workbook enables you to estimate power consumption from early design concept to design implementation. It also provides details about thermal analysis and factors that contribute to power consumption. Device resources, Flash*Freeze settings, operating frequency, clock resources, toggle rates, and many other parameters are entered into the Power Estimator workbook. These parameters are then combined with the power models to estimate the power. The power models are based on simulation or characterized device data.
| PolarFire Power Estimator | 4/2019 |
| UG0752: PolarFire FPGA Power Estimator User Guide |
2/2017 |
| SmartFusion2 and IGLOO2 Power Calculator |
1/2016 |
| SmartFusion2 and IGLOO2 Power Calculator User's Guide | 8/2014 |
| RTG4 Power Estimator | 2/2016 |
| RTG4 Power Estimator User Guide | 1/2015 |
| IGLOO Power Calculator (applicable to IGLOO, IGLOOe, and IGLOO nano) |
6/2011 |
| ProASIC3 Power Calculator (applicable to ProASIC3, ProASIC3E, ProASIC3 nano, ProASIC3L, and RT ProASIC3) |
6/2015 |
| SmartFusion Power Calculator | 9/2011 |
Additional Power Estimators and Calculators for other Microsemi FPGAs
