Low Power FPGAs

Overview

Power-optimized FPGAs 

Microsemi recently announced PolarFire cost-optimized FPGAs that deliver the lowest power at mid-range densities. PolarFire FPGAs deliver up to 50% lower power than equivalent SRAM FPGAs. During the design of the PolarFire family Microsemi specifically focused on power-optimized design choices to result in the lowest power mid-range FPGAs, to continue Micorsemi's leadership in low power for low-density and CPLD replacement devices.

These efforts result in the power numbers are shown below for PolarFire FPGAs: 

• Low device static power—34 mW for 100K LE device
• Low power transceiver lane—90 mW at 10G

PolarFire FPGAs also offer a variety of techniques and capabilities to lower the total application power. Users can take advantage of these features to lower both capital and operational expenditures with smaller or no heat sinks, smaller or fewer fans, lower cooling costs, and so on. Additionally, the lower total power advantage can also allow the user to pack more compute operations into an existing thermal budget. 

Microsemi Low Power FPGAs and SoC FPGAs

Microsemi FPGAs and SoC FPGAs have dramatically lower total power than competitive FPGAs. This is enabled by the inherent low leakage of Microsemi’s Flash-based architectures as well as no in-rush and zero-configuration current.

Microsemi FPGA families include important low power features:

• No in-rush and configuration current
• Industry’s lowest power transceivers
• Industry’s lowest static power
• ARM Cortex-M3 low power modes (SmartFusion2)
• SoC peripheral low power modes (SmartFusion2) 

No In Rush and Configuration Current

SRAM FPGAs power up in an unconfigured state and need to complete the initial power-up and reset sequence. Initially, the various configuration bits are in unknown states and need to initialize on every power cycle. Hence, a current surge is created that may generate a spike as high as several amperes for as long as a few hundred microseconds resulting in an In-rush power. To mitigate this current spike, many SRAM FPGAs have added complex power sequencing requirements to the system.

In addition to the initial in-rush power, each time an SRAM FPGA powers up a configuration cycle is required, which burns additional power as well as delaying start up of FPGA functionality everytime the device is power cycled. 

As Microsemi FPGA are non-volatile and do not need external configuration devices for reprogrammability,  Microsemi Flash FPGA eliminates hundreds of milliwatts at device startup and configuration and eliminate the need for external devices for mitigation.

Industry’s Lowest Static Power

Unlike SRAM cells used in competitors FPGAs, which are typically built using six transistors, our Flash based configuration cells (IGLOO2 example shown) are built using a single transistor, translating into exponentially lower leakage current versus SRAM cells.