VSC9800
Overview
40G CI-BCH-3 eFEC Encoder/Decoder Core and Design Package
Microsemi is a leading provider of transport processing technology with widely deployed 10G OTN Mapper devices that use enhanced FEC (eFEC). The Microsemi VSC9800 40G Continuously Interleaved BCH-3 (CI-BCH-3™) design package enables integration of eFEC encoder/decoder algorithms optimized for 40G OTN transport applications. The algorithms support the G.709 standard 6.7% FEC overhead ratio. FEC bytes are generated in the encoder using BCH (1020, 988) 3-error correcting code. FEC byte locations in the OTU3 signal are overwritten with computed CI-BCH-3™ FEC bytes.The decoder applies hard-decision CI-BCH-3™ FEC decoding to a received OTU3/3e signal. The corrected OTU3 signal is delivered at the output of the decoder. Decoding latency can be varied for FEC error-correcting performance and reduced latency tradeoffs. FEC statistic outputs such as corrected 1s, corrected 0s, and uncorrectable code words are generated for performance monitoring. The VSC9800 CI-BCH-3™ eFEC core can be targeted to FPGA or ASIC implementations including support for 100G OTU4.
Related Products
Key Features
- 40G CI-BCH-3™ eFEC
- NECG: 9.35 dB at 6.7% overhead
- Supports G.709 OTU3/3e
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