Programming and Debug

Microchip’s Programming solutions provide various programming options based on product’s life-cycle and system requirements. Various features available on-chip and in tools allow for secure remote upgrade and protection against overbuilding. The solution comprises hardware, software, and collaterals, which allow easy access to the programming and debugging features available in SoC FPGA and FPGA devices and shorten the learning curve.

PolarFire SoC,PolarFire , RTG4, SmartFusion2 , IGLOO2  ,IGLOO Series, ProASIC3 Series, SmartFusion, Fusion, ProASIC^PLUS,and Legacy & Discontinued Flash FPGA devices support programming via an external host as well as self-programming. Device can be programmed either using JTAG interface or SPI. The system controller residing inside the device handles the programming and complies to IEEE 1532 and IEEE 1149.1 JTAG standards. For SPI programming, a dedicated port SPI_SC is available.

Microsemi’s Programming solutions provide various programming options based on product’s life-cycle and system requirements. Various features available on-chip and in tools allow for secure remote upgrade and protection against overbuilding. The solution comprises hardware, software, and collaterals, which allow easy access to the programming and debugging features available in SoC FPGA and FPGA devices and shorten the learning curve.

PolarFire, SmartFusion2 and IGLOO2 devices support programming via an external master as well as self-programming. Device can be programmed either using JTAG interface or SPI. The system controller residing inside the device handles the programming and complies to IEEE 1532 and IEEE 1149.1 JTAG standards. For SPI programming, a dedicated port SPI_SC is available. 

Auto Programming – In this mode, the devices are automatically programmed by downloading the bitstream from an external SPI flash memory. The system controller configures SPI master mode and other on-chip resources to enable the programming.

Auto Update – Auto-update mode allows a pre-programmed device to be automatically programmed with an updated bitstream image if image is available in external SPI flash; whenever devices powers-up or comes out of hardware reset. This mode is also useful in field upgrades.

In-System Programming (ISP) – This mode is supported in SmartFusion2 SoC FPGA devices and allows devices to fetch programming bitstream from communication ports like USB, UART, SPI, I2C etc. Cortex-M3 core receives the bitstream and feeds to the system controller; which in-turn programs the device. This mode requires devices to have required firmware for Cortex-M3 to implement these features. This mode allows user to choose their preferred communication interface to program device in-system. 

In-Application Programming (IAP) – In this programming mode, device receives the bitstream from a host device and writes it into an external SPI flash. Or, an external SPI programmer can be used to program the SPI flash directly. Then the device verifies the content of SPI flash and goes through the programming cycle. 

Program-recovery feature is available to allow device to automatically recover from a power failure during a programming operation. It requires SPI flash to be connected to the device with a valid bitstream.

Debug Overview

Microchip  provides various debug tools to compliment design simulations and development by allowing verification and troubleshooting at the hardware level. After successful functional and post-layout simulations, Microsemi's design debug tools can help provide the designer with a pre-system level implementation early warning of other design issues.

Microsemi design debug focuses on analysis of the key elements of a flash design, such as embedded non-volatile memory (eNVM) data, SRAM data, Logic Elements, System Builder blocks. 

Microsemi provided two debugging software tools for on-chip debugging – SmartDebug and Synopsys Identify ME. 

                                                  Debug Lifecycle of an FPGA Design

Programming and Debug Tools