DSP Design Tools
Overview
Microsemi Digital Signal Processing Solution
The Microsemi DSP design flow enables the DSP designer to evaluate an algorithm at a higher level of abstraction using MATLAB and Simulink along with an exhaustive set of DSP blocksets and Microsemi IP. The DSP designer can then follow a seamless and intuitive design flow to translate, optimize, and verify the design at RTL, gate, and physical level with this industry-leading tool set. The result is very short development time and a fast time to market.
Use MATLAB® and Simulink® code generation products, including HDL Coder™ and HDL Verifier™, to accelerate the development of Microsemi FPGA designs and complete your work in days or weeks rather than months. HDL Coder and HDL Verifier work with Microsemi Libero SoC and IP to produce target-optimized implementations.
With HDL Coder and HDL Verifier, you can:
- Model, simulate, and explore your algorithms in MATLAB and Simulink
- Program Microsemi FPGAs from MATLAB and Simulink
- Verify your FPGA design against system-level specifications using HDL simulation and FPGA boards
Microsemi supports MathWorks FIL Workflow and Synphony Model Compiler ME for DSP Design flow.
Supported Product Families
Product Family |
MathWorks FIL Workflow |
Synphony Model Compiler ME* |
| PolarFire |  |
|
| RTG4 | |
|
| SmartFusion2 | |
|
| IGLOO2 | |
|
| SmartFusion | |
|
| Fusion | |
|
| IGLOO | |
|
| IGLOOe | |
|
| IGLOO PLUS | |
|
| ProASIC3 | |
|
| ProASIC3E | |
|
| ProASIC3L (including RT3PEL) | |
