MathWorks FIL Workflow - DSP and Imaging Solution
Overview
Use MATLAB® and Simulink® code generation products, including HDL Coder™ and HDL Verifier™, to accelerate the development of Microsemi FPGA designs and complete your work in days or weeks rather than months. HDL Coder and HDL Verifier work with Microsemi Libero SoC and IP to produce target-optimized implementations.
With HDL Coder and HDL Verifier, you can:
- Model, simulate, and explore your algorithms in MATLAB and Simulink
- Program Microsemi FPGAs from MATLAB and Simulink
- Verify your FPGA design against system-level specifications using HDL simulation and FPGA boards
The new Field Programmable Gate Array (FPGA)-in-the-loop (FIL) workflow integrated with MathWorks’ HDL Coder and HDL Verifier enables customers to automatically generate test benches for hardware description language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, to provide rapid prototyping and verification of designs. The new workflow is available in Mathworks’ R2018b release, giving designers the ability to integrate the MATLAB multi-paradigm numerical computing environment and the Simulink graphical programming environment with RTG4, PolarFire® FPGA and SmartFusion™2 system-on-chip (SoC) FPGA development boards.
This unified workflow integrates Microsemi’s Libero SoC & Libero SoC PolarFire Design Suite—a comprehensive, easy to learn, easy to adopt development toolset for designing with Microsemi's FPGAs and SoC FPGAs—with MATLAB and Simulink for design verification, and provides FIL verification with Microsemi FPGA boards. This allows customers to catch bugs early in the design cycle, helping reduce time to market and enabling early verification.
Generate FPGA Implementations from MATLAB, Simulink, and Stateflow
Use HDL Coder to generate VHDL and Verilog code from MATLAB, Simulink, and Stateflow®. With Simulink, you can model your algorithm using a library of more than 200 blocks. This library provides complex functions, such as the Viterbi decoder, FFT, CIC filters, and FIR filters, so you can model signal processing and communications systems and generate HDL code. Work with Fixed-Point Designer™ to convert algorithms from floating point to fixed point, and use Vision HDL Toolbox™ and LTE HDL Toolbox™ with HDL Coder to create high-level algorithmic models that you can target to Microsemi FPGAs.
Automate FPGA Verification
Reuse your MATLAB and Simulink testbench to verify your generated HDL using cosimulation with Siemens ModelSim® and Questa® simulators or Cadence Incisive and Xcelium simulators. Additionally, HDL Verifier uses FPGA-in-the-loop testing to verify hardware implementations on a variety of Microsemi FPGA development boards.
When used with HDL Verifier, HDL Coder automatically generates cosimulation and FPGA-in-the-loop models to accelerate the workflow for Microsemi FPGAs. This approach eliminates the need to manually transfer test vectors and helps identify errors earlier in the FPGA design process.
Click here to learn more about how you can get started, including an archived webinar on targeting algorithms to our FPGAs.
