Programming
Overview
Programming Hardware & Software
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Programming Info
Microsemi’s Programming solutions provide various programming options based on product’s life-cycle and system requirements. Various features available on-chip and in tools allow for secure remote upgrade and protection against overbuilding. The solution comprises hardware, software, and collaterals, which allow easy access to the programming and debugging features available in SoC FPGA and FPGA devices and shorten the learning curve.
PolarFire, SmartFusion2 and IGLOO2 devices support programming via an external master as well as self-programming. Device can be programmed either using JTAG interface or SPI. The system controller residing inside the device handles the programming and complies to IEEE 1532 and IEEE 1149.1 JTAG standards. For SPI programming, a dedicated port SPI_SC is available.
Auto Programming – In this mode, the devices are automatically programmed by downloading the bitstream from an external SPI flash memory. The system controller configures SPI master mode and other on-chip resources to enable the programming.
Auto Update – Auto-update mode allows a pre-programmed device to be automatically programmed with an updated bitstream image if image is available in external SPI flash; whenever devices powers-up or comes out of hardware reset. This mode is also useful in field upgrades.
In-System Programming (ISP) – This mode is supported in SmartFusion2 SoC FPGA devices and allows devices to fetch programming bitstream from communication ports like USB, UART, SPI, I2C etc. Cortex-M3 core receives the bitstream and feeds to the system controller; which in-turn programs the device. This mode requires devices to have required firmware for Cortex-M3 to implement these features. This mode allows user to choose their preferred communication interface to program device in-system.
In-Application Programming (IAP) – In this programming mode, device receives the bitstream from a host device and writes it into an external SPI flash. Or, an external SPI programmer can be used to program the SPI flash directly. Then the device verifies the content of SPI flash and goes through the programming cycle.
Program-recovery feature is available to allow device to automatically recover from a power failure during a programming operation. It requires SPI flash to be connected to the device with a valid bitstream.
Secure Programming
Cryptographic design security in Microsemi FPGAs and SoC FPGA provide information security of the configuration data. It is the assurance that the user design is secure and operates as intended for the life of the product. PolarFire, SmartFusion2 and IGLOO2 devices have built-in features that provide enhanced security during all stages of the device lifecycle: from wafer probe and initial Microsemi provisioning of factory keys and certificates, to assurances that the supply chain has delivered genuine devices to the user, to user key injection and bitstream programming, to field updates, and finally to device decommissioning.
There are three user programmable sub-blocks within the SmartFusion2 and IGLOO2 FPGA devices. The FPGA fabric contains configurable user logic and can be programmed independently of other blocks. The eNVM block is user non-volatile flash memory and can also be programmed independently. There are two separate groups of security segments (factory and user) that are tamper protected blocks used to safely store factory and user security keys as well as configurable security settings. All programming operations including programming, verification, and security key management are managed by the system controller.
Secure Bitstream Loading – Microsemi’s FPGA devices are configured using a Microsemi proprietary and confidential format bitstream file. These are always loaded as encrypted source, with the associated keys being protected by patented DPA countermeasures. All bitstreams are encrypted using the Advanced Encryption Standard (AES) symmetric cipher with 256-bit keys, and then an authentication tag is added based on the Secure Hash Algorithm (SHA-256). No plain text bitstream format is supported by SmartFusion2 and IGLOO2 FPGA devices or the associated EDA tools that prepare bitstreams targeted to it.
Version Control - The SmartFusion2 and IGLOO2 FPGA devices have an option of preventing any back-tracking of configuration files. This allow only programming bitstreams with design version greater than the currently configured “Back Level”.
Programming Tools
FlashPro
The Microsemi FlashPro programming system is a combination of FlashPro software and hardware programmer. Together they provide ISP for flash-based FPGA devices: PolarFire, IGLOO2, SmartFusion2, RTG4, IGLOO/e, ProASIC3 (including RT ProASIC3), SmartFusion, Fusion, and ProASICPLUS families.
FlashPro programming software is bundled with Libero SoC and available for standalone download also. The programming software is available in two variants:
- FlashPro Software for Window only
- FlashPro Express Software available for both Windows and Linux
Microsemi provides hardware programmers for ISP. These hardware programmers are used with Microsemi’s FlashPro software. FlashPro series of hardware programmers save the board space as a single JTAG chain can be used for all JTAG devices. ISP using JTAG port adds the flexibility of field upgrades or post-assembly production-line characterization. Production cost is significantly reduced as a result of the elimination of expensive sockets on the board.
Silicon Sculptor
Silicon Sculptor is an FPGA programming tool that delivers high data throughput and promotes ease of use while lowering the overall cost of ownership.
Programmer |
Supported Device |
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FlashPro6 |
PolarFire, SmartFusion2, IGLOO2, and RTG4 |
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FlashPro5 |
PolarFire FPGA, SmartFusion2 SoC FPGAs, IGLOO2 FPGAs, ProASIC3\e FPGAs, ProASIC3 nano FPGAs, IGLOO/e FPGAs, IGLOO PLUS FPGAs,IGLOO nano FPGAs, Fusion Mixed-Signal FPGAs, SmartFusion SoC FPGAs |
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FlashPro4 |
PolarFire FPGA, SmartFusion2 SoC FPGAs, IGLOO2 FPGAsProASIC3\e FPGAs, ProASIC3 nano FPGAs, IGLOO/e FPGAs, IGLOO PLUS FPGAs,IGLOO nano FPGAs, Fusion Mixed-Signal FPGAs, SmartFusion SoC FPGAs |
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FlashPro Lite |
ProASICPLUS |
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Silicon Sculptor 4 |
Click here for more information |
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DirectC / SPI-DirectC
DirectC and SPI-DirectC are embedded In-System Programming (ISP) solutions for Microsemi’s FPGAs and SoC FPGAs that support JTAG and SPI slave mode programming mode respectively. Package contains ANSI C compliant C code to support programming along with the sample project and documentaiton. DirectC and SPI-DirectC can be used by making minor modifications to the source code, adding the necessary application programming interface (API), and compiling the source code and the API together to create a binary executable.
STAPL Player
The standard test and programming language (STAPL) Player may be used to program ProASICPLUS and third-generation flash devices such as IGLOO, ProASIC3, ProASIC3L, Fusion, and interprets the contents of a STAPL file generated by Microsemi's Libero IDE and Designer software tools. The file contains information about the programming of ProASICPLUS devices and JTAG scan chain for a single device. The data format is a JEDEC standard known as the STAPL format. The STAPL Player reads the STAPL file and executes the file's programming instructions. As all programming details are in the STAPL file, the STAPL Player is device-independent.