Clock Fan-out Buffers

Overview

Microsemi’s portfolio of miClockBuffer™ and miSmartBuffer™ of devices are synergistic with Microsemi's industry leading timing portfolio —when combined, they can create a simplified, more reliable, and low-cost complete clock tree that replaces many on-board multipliers, synthesizers, and oscillators.

Clock Fanout Buffer Product Preview Clock Fanout Buffer Selector Guide miClockManagement Product Preview

LVDS/LVPECL/HCSL and LVCMOS miSmartBuffers - ZL4023x, ZL4024x, ZL4025x

Microsemi’s miSmartBuffer ZL4025x family of devices is differentiated from traditional fan-out buffers by compelling features for data center, communications, optical, storage, and networking applications. The ZL4025x family of devices enable creation of multiple clock signal copies that can be distributed among several loads with minimal additive jitter. miSmartBuffer™ ZL4025x Family Product Preview

Microsemi’s miClockBuffer and miSmartBuffer ZL4023x and ZL4024x family provides customers with a variety of configurations includinging up to 10 highly flexible single-ended and differential outputs (I/Os) , per output control through a serial port or hardware pins, ultra-low additive jitter and power supply noise suppression.

LVDS/LVPECL/HCSL and LVCMOS miClockBuffers - ZL4023x, ZL4024x, ZL4026x

Microsemi’s miClockBuffer ZL4023x, ZL4024x, ZL4026x family provides customers with a variety of configurations including up to 10 highly flexible single-ended and differential outputs (I/Os) and per output control through hardware pins, ultra-low additive jitter and power supply noise suppression.

LVPECL miClockBuffers - ZL402XX

Microsemi’s miClockBuffer ZL402xx LVPECL family of buffers supports clock rates of up to 750 megahertz (MHz with inputs are compatible with LVPECL, LVDS, CML, HCSL, LVCMOS, HSTL and SSTL while offering six fanout combinations including 1:2, 1:4, 1:6, 1:8, 2:6 and 2:8 and Internal and external terminations

LVDS miClockBuffers - ZL402XX

Microsemi’s miClockBuffer ZL402xx LVDS family of buffers supports clock rates of up to 750 megahertz (MHz with inputs are compatible with LVPECL, LVDS, CML, HCSL, LVCMOS, HSTL and SSTL while offering six fanout combinations including 1:2, 1:4, 1:6, 1:8, 2:6 and 2:8 and Internal and external terminations

Microchip Clock and Data Distribution

Microchip offers one of the most extensive arrays of clock distribution product lines in the industry. Ranging from 2 to 22 outputs, they support differential (LVPECL, LVDS, HCSL, CML) and single-ended CMOS outputs, and have a maximum clock rate of 7.0 GHz and data rate of 10.7 Gbps, with very low additive jitter. Microchip’s clock distribution family consist of TCXO fanout buffers, crystal or reference input fanout buffers, signal translators, cross-point switches, high-performance clock dividers, receiver-buffer drivers, multiplexers, delay lines and logic gates.

Fan Out Buffers 2 - 22 outputs offered PECL/LVDS/HCSL/CMOS Up to 7.0 GHz clock rate & 10.7 Gbps data rate	Drivers & Receivers PECL/LVPECL/CML/LVDS Up to 7.0 GHz clock rate & 10.7 Gbps data rate	Zero-Delay Buffers High perf. low skew, low jitter Distributes high speed and spread spectrum clocks
PCIe Buffers Gen 1, 2, 3 compliant 2 - 19 outputs	Dividers Divide by 1, 2, 3, 4, 5, 8, 16 Multiple Output Banks Single-Ended & Differential PECL/LVPECL/CML/LVDS	Logic Translators Clock or data rates up to 7 GHz Conversion from single-ended to diff.
Multiplexers Up to 16 input Max PECL/LVPECL/CML/LVDS Up to 7.0 GHz clock rate & 10.7 Gbps data rate	Crosspoint Switches Single & Dual Channel Up to 6 GHz clock rate & 10.7 Gbps data rate CML/LVDS	Backplane & Cable Pre-Emphasis and Equalization Single-Ended & Differential Up to 6.4Gbps CML Output
Skew Management 2.2 - 13.2ns Programmable delay 10ps delay increments Fine Tune Control Chip Cascading: extend delay	Flip-Flops & Logic Gates D flip-flops: CML Output Logic Gates