MX

Overview

Featuring very low power consumption and the industry's highest design security, MX FPGAs offer designers a reliable, single-chip ASIC alternative. Providing an efficient, flexible 5.0 V architecture, MX is an ideal platform for integrating your legacy PLDs into a single, low-cost device. MX is a high-volume platform that enables solutions without compromising on cost and time.

Key Features

High-performance mixed-voltage solution
PCI compliant
Contains embedded dual-port SRAM modules
Available in military and automotive temperature grades

Product Tables

Product Family

Please refer to the ordering tab for a list of all available part numbers.

Device	A40MX02	A40MX04	A42MX09	A42MX16	A42MX24	A42MX36
Capacity
System Gates	3,000	6,000	14,000	24,000	36,000	54,000
SRAM Bits						2,560
Logic Modules
Sequential			348	624	954	1,230
Combinatorial	295	547	336	608	912	1,184
Decode					24	24
Clock-to-Out	9.5 ns	9.5 ns	5.6 ns	6.1 ns	6.1 ns	6.3 ns
SRAM Modules (64x4 or 32x8)						10
Dedicated Flip-Flops			348	624	954	1,230
Clocks	1	1	2	2	2	6
Maximum Flip-Flops	147	273	516	928	1,410	1,822
User I/O (maximum)	57	69	104	140	176	202
PCI					Yes	Yes
Boundary Scan Test (BST)					Yes	Yes
Speed Grades	-F, Std., -1, -2, -3	-F, Std., -1, -2, -3	-F, Std., -1, -2, -3	-F, Std., -1, -2, -3	-F, Std., -1, -2, -3	-F, Std., -1, -2, -3
Temperature Grades	C, I, M, A	C, I, M, A	C, I, M, A	C, I, M, A	C, I, M, A	C, I, M, A, B
Packages (by pin count)
PLCC	44, 68	44, 68, 84	84	84	84
PQFP	100	100	100, 144, 160	100, 160, 208	160, 208	208, 240
VQFP	80	80	100	100
TQFP			176	176	176
CQFP						208, 256
PBGA						272
CPGA			132

Documents

Datasheets User's Guides & Manuals Application Notes Product Information Brochures (PIB) Other Documents

Datasheets

DS2136 : 40MX and 42MX FPGA Families Datasheet (includes Military/Aerospace information)	2.4 MB	8/2017
DS0025: 40MX and 42MX Automotive FPGA Families Datasheet	2.5 MB	12/2016

Packaging Data

Package Mechanical Drawings	11 MB	5/2015
Package Thermal Characteristics and Weights	388 KB	11/2012
Hermetic Package Mechanical Configuration	24 KB	11/2003

User's Guides and Manuals

DC-DC Regulator Guide for Microsemi SoC FPGAs and FPGAs

379 KB

3/2013

Application Notes

AC308: Antifuse MetaReport AN		5.93 MB	2/2015
AC399: Migrating from ACT1 to 40MX Family FPGAs App Note		757 KB	11/2014
AC405: Migrating from ACT2 Devices to 42MX Family FPGAs App Note		1.05 MB	11/2014
AC420: Migrating from ACT3 Devices to 42MX Family FPGAs App Note		800 KB	4/2014
AC225: Programming Antifuse Devices App Note	678 KB	11/2011
AC276: Board Level Considerations for Microsemi FPGAs App Note		883.7 KB	8/2012
AC297: Migrating from 1200XL and 3200DX to 42MX FPGAs App Note Migrate to MX Design Files (ZIP, 4 KB, 01/07)	302 KB	1/2007
AC291: 42MX Family Devices Power-Up Behavior App Note	662 KB	08/2015
AC141: MP3 Personal Digital Players Using Microsemi FPGAs App Note	211 KB	9/2000
AC133: Benefits of the MX Family of Devices App Note	30 KB	9/1998

Product Information Brochures (PIB)

Antifuse Product Catalog

6.11 MB

1/2020

Design Resources

Design Software	The MX family of FPGAs are fully supported by Microsemi Libero Integrated Design Environment (IDE), a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration, as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment.
Programming & Debug	MX FPGAs are supported by Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI, provides programming support. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, enables designers to examine any of the internal nodes of a device operating in a prototype or a production system.
IP Cores	Search for MX IP cores
Partners	Many of Microsemi’s Partners are engaged in development with MX devices
IBIS Models	Generic MX IBIS Models are available for signal integrity simulations. Design specific files can also be exported from your design implementation in Libero.
BSDL Models	Generic MX BSDL Models are available for boundary scan testing. Design specific files can also be exported from your design implementation in Libero.

Product Selector Guide

Featuring very low power consumption and the industry’s highest design security, MX FPGAs offer designers a reliable, single-chip ASIC alternative. MX devices provide high performance while shortening the system design and development cycle. Offering an efficient, flexible 5.0 V architecture, MX is an ideal high-volume platform for integrating your legacy PLDs into a single device. Example applications include high-speed controllers and address decoding, peripheral bus interfaces, DSP and coprocessor functions.

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MX