eX

Overview

With a focused combination of features, eX can meet all of your power, speed, package, and price requirements. Optimized for wired and mobile e-appliances, eX enables designers to use a flexible single-chip FPGA for their traditional low-density ASIC requirements without the long lead times and costly NRE charges.

Key Features

Low power consumption
Live at power-up
2.5 V, 3.3 V, and 5.0 V mixed-voltage operation with 5.0 V input tolerance and 5.0 V drive strength
Up to 100% resource utilization with 100% pin locking
Fuselock secure programming technology prevents reverse engineering and design theft
Available in automotive temperature grades

Product Tables

Product Family

Please refer to the ordering tab for a list of all available part numbers.

Device	eX64	eX128	eX256
Capacity
System Gates	3,000	6,000	12,000
Typical Gates	2,000	4,000	8,000
Register Cells
Dedicated Flip-Flops	64	128	256
Maximum Flip-Flops	128	256	512
Combinatorial Cells	128	256	512
Maximum User I/Os	84	100	132
Global Clocks
Hardwired	1	1	1
Routed	2	2	2
Speed Grades	-F, Std., -P	-F, Std., -P	-F, Std., -P
Temperature Grades¹	C, I, A	C, I, A	C, I, A
Package (by pin count)
TQFP	64	64, 100	100

Note:

Refer to the eX Automotive Family FPGAs datasheet for details on automotive temperature offerings.

Documents

Datasheets User's Guides & Manuals Application Notes Product Information Brochures (PIB)
Other Documents White Papers Power Calculator FAQ

Datasheets

eX Datasheet (Revision 10)	2 MB	10/2012
eX Automotive Family FPGAs Datasheet Revision 5	2 MB	10/2012

Packaging Data

Package Mechanical Drawings	11 MB	5/2015
Package Thermal Characteristics and Weights	388 KB	11/2012
Hermetic Package Mechanical Configuration	24 KB	11/2003

User's Guides and Manuals

DC-DC Regulator Guide for Microsemi SoC FPGAs and FPGAs

379 KB

3/2013

Application Notes

AN4535: Programming Antifuse Devices	160 KB	5/2022
AC160: IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families App Note	1 MB	5/2012
AC200: Microsemi eX, SX-A and RTSX-S I/Os App Note	853 KB	4/2012
AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note Library Files (ZIP, 1.62 KB, 3/12)	708 KB	3/2012
AC308: Antifuse MetaReport AN		5.93 MB	2/2015
AC373: Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note Design Files (ZIP, 5.1 MB, 11/11)	2 MB	11/2011
AC276: Board Level Considerations for Microsemi FPGAs App Note		883.7 KB	8/2012
AC379: Advanced Static Timing Analysis Using SmartTime App Note	6 MB	11/2011
AC225: Programming Antifuse Devices App Note	678 KB	11/2011
AC140: Design for Low Power in Microsemi Antifuse FPGAs App Note	155 KB	9/2000

Product Information Brochures (PIB)

Antifuse Product Catalog

6.11 MB

1/2020

White Papers

Jitter and Phase Noise Analysis of Microsemi's eX Devices

2 MB

5/2003

Power Calculator

eX, SX-A and RT54SX-S Power Calculator

853 KB

2/2012

FAQ

eX Device FAQ

150 KB

10/2002

Design Resources

Design Software	The eX family of FPGAs are fully supported by Microsemi Libero Integrated Design Environment (IDE), a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration, as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment.
Programming & Debug	eX FPGAs are supported by Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI, provides programming support. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, enables designers to examine any of the internal nodes of a device operating in a prototype or a production system.
IP Cores	Search for eX IP cores
Partners	Many of Microsemi’s Partners are engaged in development with eX devices
Power Analysis	Leverage our Excel based eX Power Calculator to evaluate power for your design without running through the full design flow. SmartPower can also provide design specific power analysis for your design implementation within Libero.
IBIS Models	Generic IBIS Models: SX-A/eX are available for signal integrity simulations. Design specific files can also be exported from your design implementation in Libero.
BSDL Models	Generic eX BSDL Models are available for boundary scan testing. Design specific files can also be exported from your design implementation in Libero.

Product Selector Guide

The eX family of FPGAs, with its focused combination of features, can meet all of your power, speed, package and price requirements. eX devices are optimized for wired and mobile e-appliances, and enable designers to use a flexible single-chip FPGA for their traditional low-density ASIC requirements without the long lead times and costly NRE charges.

Registered Users & Partners

How to Buy

Company

Solution Partners

Quality & Packaging

eX