SX-A

Overview

Microsemi SX-A devices can match the speed and performance of an ASIC. SX-A devices can be used to generate system-wide savings by integrating multiple functions into a low cost, single-chip solution. Providing a combination of performance, security, and low power, SX-A decreases the premium for performance while providing a solution highly secure from reverse engineering.

12,000 to 108,000 usable system gates
350 MHz internal clock frequency
66 MHz, 64-bit 3.3 V / 5.0 V PCI performance (supporting Target, Master and Master/Target)
2.5 V, 3.3 V, and 5.0 V mixed-voltage support
100% resource utilization with 100% pin locking
Available in military and automotive temperature grades

SX devices have been classified as a "legacy" device. For more information, visit the Legacy & Discontinued Antifuse FPGAs page.

Product Tables

Product Family

Please refer to the ordering tab for a list of all available part numbers.

Device	A54SX08A	A54SX16A	A54SX32A	A54SX72A
Capacity
Typical Gates	8,000	16,000	32,000	72,000
System Gates	12,000	24,000	48,000	108,000
Logic Modules	768	1,452	2,880	6,036
Combinatorial Cells	512	924	1,800	4,024
Dedicated Flip-Flops	256	528	1,080	2,012
Maximum Flip-Flops	512 *	990	1,980	4,024
Maximum User I/Os	130	180	249	360
Global Clocks	3	3	3	3
Quadrant Clocks	0	0	0	4
Boundary Scan Testing	Yes	Yes	Yes	Yes
JTAG
3.3 V / 5 V PCI	Yes	Yes	Yes	Yes
Clock-to-Out
Input Set-Up (External)	0 ns	0 ns	0 ns	0 ns
Speed Grades	-F, Std., -1, -2	-F, Std., -1, -2	-F, Std., -1, -2	-F, Std., -1, -2
Temperature Grades	C, I, A, M	C, I, A, M	C, I, A, M, B	C, I, A, M, B
Package (by pin count)
PQFP	208	208	208	208
TQFP	100, 144	100, 144	100, 144, 176
PBGA			329
FBGA	144	144, 256	144, 256, 484	256, 484
CQFP			84, 208, 256	208, 256

Note: * A maximum of 512 registers is possible if all 512 C-cells are used to build an additional 256 registers.

Documents

Datasheets User's Guides & Manuals Application Notes
Product Information Brochures (PIB) Power Calculator FAQ

Datasheets

SX-A Family FPGAs Datasheet v5.3 (includes Military Temperature Plastic Devices)	765 KB	2/2007
HiRel SX-A Family FPGAs Datasheet v2.0 (includes Military Temperature Hermetic and MIL-STD-883 Class B Devices)	437 KB	11/2006
SX-A Automotive Family FPGAs Datasheet v2.2	498 KB	6/2006

Packaging Data

Hermetic Package Mechanical Configuration	24 KB	11/2003
Package Mechanical Drawings	11 MB	5/2015
Package Thermal Characteristics and Weights	388 KB	11/2012

User's Guides and Manuals

DC-DC Regulator Guide for Microsemi SoC FPGAs and FPGAs

379 KB

3/2013

Application Notes

AN4535: Programming Antifuse Devices	160 KB	5/2022
AC148: Using Microsemi's A54SX08A FPGA to Interface a PowerQUICC Microprocessor to a MUSIC-IC LANCAM App Note	109 KB	7/2001
AC150: Using External SRAM Memory with Microsemi SX/SX-A FPGAs App Note	126 KB	8/2001
AC157: SX to SX-A Migration App Note	85 KB	5/2002
AC158: Microsemi SX-A and RTSX-SU Devices in Hot-Swap and Cold-Sparing Applications App Note	1 MB	9/2012
AC160: IEEE Standard 1149.1 (JTAG) in the SX/RTSX/SX-A/eX/RT54SX-S Families App Note	1 MB	5/2012
AC161: Using Schmitt Triggers for Low Slew-Rate Input App Note	218 KB	11/2002
AC169: Using A54SX72A and RT54SX72S Quadrant Clocks App Note	582 KB	2/2003
AC200: Microsemi eX, SX-A and RTSX-S I/Os App Note	853 KB	4/2012
AC201: Maximizing Logic Utilization in eX, SX, and SX-A FPGA Devices Using CC Macros App Note Library Files (ZIP, 1.62 KB, 3/12)	708 KB	3/2012
AC225: Programming Antifuse Devices App Note	678 KB	11/2011
AC255: Microsemi Recommendations for Programming RTSX-S, RTSX-SU, and SX-A Technical Brief	172 KB	4/2006
AC263: Simultaneous Switching Noise and Signal Integrity Application Note	273 KB	2/2018
AC276: Board Level Considerations for Microsemi FPGAs App Note	883.7 KB	8/2012
AC308: Antifuse MetaReport AN	5.93 MB	2/2015
AC373: Source-Synchronous Clock Designs: Timing Constraints and Analysis App Note Design Files (ZIP, 5.1 MB, 11/11)	2 MB	11/2011
AC379: Advanced Static Timing Analysis Using SmartTime App Note	6 MB	11/2011

Product Information Brochures (PIB)

Antifuse Product Catalog

6.11 MB

1/2020

Power Calculator

eX, SX-A and RT54SX-S Power Calculator

853 KB

2/2012

FAQ

SX-A Device FAQ

493 KB

6/2005

Design Resources

Design Software	The SX-A family of FPGAs are fully supported by Microsemi Libero Integrated Design Environment (IDE), a design management environment that guides the user through the FPGA design flow and provides seamless design tool integration, as well as project, data file, and log file management. Libero IDE enables users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment.
Programming & Debug	Axcelerator FPGAs are supported by Silicon Sculptor 3, a single-site programmer driven via a PC-based GUI, provides programming support. Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, enables designers to examine any of the internal nodes of a device operating in a prototype or a production system.
IP Cores	Search for SX-A IP cores
Partners	Many of Microsemi’s Partners are engaged in development with SmartFusion devices
Power Analysis	Leverage our Excel based SX-A Power Calculator to evaluate power for your design without running through the full design flow. SmartPower can also provide design specific power analysis for your design implementation within Libero.
IBIS Models	Generic SX-A IBIS Models are available for signal integrity simulations. Design specific files can also be exported from your design implementation in Libero.
BSDL Models	Generic SX-A BSDL Models are available for boundary scan testing. Design specific files can also be exported from your design implementation in Libero.

Product Selector Guide

The SX-A family of FPGAs offers a cost-effective, single-chip solution for low-power, high-performance designs. SX-A devices can be used to generate system-wide savings by integrating multiple functions into a single-chip solution. Providing a combination of performance, security and low power, SX-A FPGAs decrease the premium for performance while providing a solution that is highly resistant to reverse engineering.

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