Axcelerator
Overview
The latest antifuse FPGA family offered by Microsemi, Axcelerator® offers high performance and unprecedented design security at densities of up to 2 million equivalent system gates.
Utilizing the Microsemi AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic.
Based upon 0.15 µm, seven-layers-of-metal CMOS antifuse process technology, Axcelerator devices offer a level of performance previously only available in ASIC technology.
Key Features
- 350 MHz system performance
- 500+ MHz internal performance
- 500+ MHz embedded FIFOs
- PLL output up to 1 GHz and 8 PLLs per device
- 6 levels of logic at 156+ MHz
- 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
- 8 I/O banks per device
- 8 global clocks per device
- 4.5 kbits variable-aspect RAM blocks with built-in FIFO control
- Intelligent low power operation
- Secure programming technology prevents reverse engineering and design theft
- Available in military temperature grades
Target Applications
- Consumer: Smartphones, GPS, high-end digital cameras, PDA, wireless gadgets, portable media players
- Industrial: Point of sale, scanners, portable printers, RFID readers, portable radios, portable test and measurement equipment
- Medical: Dental, medical instrumentation, defibrillators, insulin pump
- Automotive: Car RF tag, instrumentation controls
- Computing: Modules for laptops, PCMCIA cards
- Telecomm: Wired and wireless electronics with high performance requirements
- Military/Aerospace: Flight computers, mission computers, weapon systems, radar control systems
Product Tables
Product Family
Please refer to the ordering tab for a list of all available part numbers.
| Device | AX125 | AX250 | AX500 | AX1000 | AX2000 |
|---|---|---|---|---|---|
| Capacity (in Equivalent System Gates) | 125,000 | 250,000 | 500,000 | 1,000,000 | 2,000,000 |
| Typical Gates | 82,000 | 154,000 | 286,000 | 612,000 | 1,060,000 |
| Modules | |||||
| Register (R-cells) | 672 | 1,408 | 2,688 | 6,048 | 10,752 |
| Combinatorial (C-cells) | 1,344 | 2,816 | 5,376 | 12,096 | 21,504 |
| Maximum Flip-Flops | 1,344 | 2,816 | 5,376 | 12,096 | 21,504 |
| Embedded RAM/FIFO | |||||
| Number of Core RAM Blocks | 4 | 12 | 16 | 36 | 64 |
| Total Bits of Core RAM | 18,432 | 55,296 | 73,728 | 165,888 | 294,912 |
| Clocks (Segmentable) | |||||
| Hardwired | 4 | 4 | 4 | 4 | 4 |
| Routed | 4 | 4 | 4 | 4 | 4 |
| PLLs | 8 | 8 | 8 | 8 | 8 |
| I/Os | |||||
| I/O Banks | 8 | 8 | 8 | 8 | 8 |
| Maximum User I/Os | 168 | 248 | 336 | 516 | 684 |
| Maximum LVDS Channels | 84 | 124 | 168 | 258 | 342 |
| Total I/O Registers | 504 | 744 | 1,008 | 1,548 | 2,052 |
| Speed Grades | Std., -1, -2 | Std., -1, -2 | Std., -1, -2 | Std., -1, -2 | Std., -1, -2 |
| Temperature Grades | C, I | C, I, M | C, I, M | C, I, M | C, I, M |
| Package | |||||
| PQFP | 208 | 208 | |||
| BGA | 729 | ||||
| FBGA | 256, 324 | 256, 484 | 484, 676 | 484, 676, 896 | 896, 1152 |
| CQFP | 208, 352 | 208, 352 | 352 | 256, 352 | |
| CCGA/LGA | 624 | 624 | |||
Documents
Datasheets User's Guides & Manuals Application Notes Product Briefs Product Information Brochures (PIB) Power Calculator
| Axcelerator Family FPGAs Datasheet (includes Military/Aerospace information) |
13 MB | 3/2012 |
Packaging Data
| Hermetic Package Mechanical Configuration | 24 KB | 11/2003 |
| Package Mechanical Drawings | 11 MB | 5/2015 |
| Package Thermal Characteristics and Weights | 388 KB | 11/2012 |
| DC-DC Regulator Guide for Microsemi SoC FPGAs and FPGAs | 379 KB | 3/2013 |
| Axcelerator Family FPGAs Product Brief | 327 KB | 10/2009 |
Product Information Brochures (PIB)
| Antifuse Product Catalog | 491 KB | 8/2013 |
| AX and RTAX-S/SL/D Power Calculator |  |
436 KB | 1/2011 |
Design Resources
| Design Software |
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| Programming & Debug |
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| IP Cores | |
| Partners |
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| IBIS Models |
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| BSDL Models |
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Product Selector Guide
The Axcelerator FPGA family is a single-chip, nonvolatile solution offering high performance and unprecedented design security at densities of up to 2 million equivalent system gates. Utilizing the AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing and carry logic. The solution is based upon 0.15 μm, seven-layers-of-metal CMOS antifuse process technology and 350 MHz system performance.
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