Verification and Optimization
Overview
SmartPower identifies static and dynamic power consumption problems quickly within a design. It can operate hierarchically to estimate the power consumption of individual components or events, rather than being restricting to the overall design. This dramatically simplifies power analysis over other, non-hierarchical, tools. SmartPower generates detailed hierarchical reports of the dynamic power consumption of a design for easy inspection using a simple graphical user interface, as illustrated in the figure below. The Summary tab shows the overall Power Consumption for both Static and Dynamic power. A more detailed Breakdown is given in the pie chart (or via a grid) in the middle of the screen. Annotation Coverage and Operating Conditions are also available for viewing. For battery-powered designs an additional capability can be used to define the low power modes of the design, determines the power profile and calculates the expected battery lifetime.
Key Features List
- SmartPower provides a hierarchical view of Power Consumption to simplify the identification of design ‘hot spots’
- Analysis of nets, gates, I/Os, memories, clocks, cores, clock domains, power supply rails, peak power during a clock cycle, and switching transitions
- Generated reports include design-level power summary, average switching activity, and ambient and junction temperature readings
- Reports also include the various components of the design, the power analysis methodology used and the coverage percentage
- Can simulate maximum process characteristics for Process, Voltage and Temperature
- Multiple input sources
- IEEE 1364 Standard VCD file
- Synopsys Switching Activity Interchange Format (SAIF)
- SmartPower internal vector-less estimation process
- Additional Capabilities for Battery operated Designs
- Power Profile allows the measurement of power and battery life
- Define multiple power operating modes and timing duration
- I/O Advisor feature suggests changes to output loads, drive strengths, and slew rates to help reduce power consumption taking into account timing constraints
For more details, refer SmartPower user guide available at Libero SoC page
Verification
Design verification and debug are critical steps of the FPGA design flow. Microsemi offers many tools to support these activities.
- Mentor Graphics ModelSim ME for pre and post layout simulation
- Microsemi SmartDebug for hardware debug
- Microsemi FPGA On-Chip Debug Tools for hardware debug
- Synopsys Identify ME internal logic analyzer