BSDL Models
Overview
To view Generic BSDL models, please choose one of the following families:
FPGAs
SoC FPGAs |
Rad-Tolerant FPGAsAntifuse FPGAsLegacy & Discontinued Devices |
ACT 1 / ACT 2 / ACT 3 / 1200XL: The BSDL for these devices are not available as these families do not support JTAG Boundary Scan. For more information, please review the Microsemi BSDL Files Format Descriptionapplication note.
Notes
-
The BSDL files contained herein are Generic BSDL only. The Microsemi Libero software currently supports the exporting of Design-Specific BSDL for the PolarFire, SmartFusion2, IGLOO2, IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, ProASIC3 nano, ProASIC3L, SmartFusion, Fusion, SX-A, eX, SX, RTG4, RTAX-S/SL, RT ProASIC3, RTSX-S, RTSX, ProASICPLUS and ProASIC families.
-
While doing boundary scan testing of a programmed device, the I/Os are defined per design (use design-specific BSDL). I/Os of an unprogrammed device have default state: LVTTL 3.3 V, lowest drive strength, slow slew, and weak pull-up enabled (where applicable). This default state can be overridden by IOCONFIG instruction.
- All BSDL files are syntax checked using Agilent Technologies syntax checker tool.