LVDS_TX_7_1 |
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Overview
The MIV_RV32IMC is a processor core designed to implement the RISC-V instruction set for use in Microchip FPGAs. The core includes an industry standard JTAG interface to facilitate debug access. Three optional bus interfaces are available for peripheral and memory accesses. They are AHB, APB3, and AXI which can be configured as AXI3 or AXI4.
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Alphanumeric Parameter | Value |
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Core Provider | Microchip |
Functional Category | Bus Interfaces |
Device Family | IGLOO2,SmartFusion2 |
Application | Aerospace,Automotive,Industrial,Medical |
This part can be found in the following product categories: